ADITI SHINDE CHIDAMBARAM ALAGAPPAN

Slides:

Advertisements

Similar presentations

1 Lecture 3: MIPS Instruction Set Today’s topic:  More MIPS instructions  Procedure call/return Reminder: Assignment 1 is on the class web-page (due.

Advertisements

Adding the Jump Instruction

1 Datapath and Control (Multicycle datapath) CDA 3101 Discussion Section 11.

CIS 314 Fall 2005 MIPS Datapath (Single Cycle and Multi-Cycle)

ELEN 468 Advanced Logic Design

Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay.

{ CPU Design-Project CPU Design-Project Multicycle Datapath with Finite State Machine as Control Unit N.S.V Ravi Tej Uppu.

PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op +4 shift 2 zero BRANCH CTRL muxmux sign extend immed 1632 ADDADD.

VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Fall 2007 MIPS Datapath (Single Cycle and Multi-Cycle)

Computer Engineering AddSub page 1 Basic Building Blocks Multiplexer + Demultiplexer Adder.

1 COMP541 Multicycle MIPS Montek Singh Apr 4, 2012.

CDA 3101 Fall 2013 Introduction to Computer Organization Multicycle Datapath 9 October 2013.

Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

W.S Computer System Design Lecture 4 Wannarat Suntiamorntut.

COMP541 Multicycle MIPS Montek Singh Mar 25, 2010.

EE 3755 Datapath Presented by Dr. Alexander Skavantzos.

By Wannarat Computer System Design Lecture 4 Wannarat Suntiamorntut.

ECE-C355 Computer Structures Winter 2008 The MIPS Datapath Slides have been adapted from Prof. Mary Jane Irwin ( )

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

Multicycle datapath.

COM181 Computer Hardware Lecture 6: The MIPs CPU.

Pipeline Processor Design Project Jarred Beck. Design Assumptions Three bit opcode This is to be able to address all of the 8k memory directly =

Design a MIPS Processor (II)

Single-cycle CPU Control

Access the Instruction from Memory

EE204 Computer Architecture

CS Computer Architecture Week 10: Single Cycle Implementation

Single Cycle CPU - Control

CS161 – Design and Architecture of Computer Systems

Electrical and Computer Engineering University of Cyprus

Chapter 5: A Multi-Cycle CPU.

CS161 – Design and Architecture of Computer Systems

Example Addiu $t1 $r0 3 Addiu $t1 $t1 5 Addiu $t1 $t1 7.

ELEN 468 Advanced Logic Design

Multi-Cycle CPU.

Extensions to the Multicycle CPU

Single Cycle Processor

Multi-Cycle CPU.

CS/COE0447 Computer Organization & Assembly Language

MIPS processor continued

CSCI206 - Computer Organization & Programming

CS/COE0447 Computer Organization & Assembly Language

CSCE 212 Chapter 5 The Processor: Datapath and Control

Single-Cycle CPU DataPath.

CS/COE0447 Computer Organization & Assembly Language

Vishwani D. Agrawal James J. Danaher Professor

MIPS Processor.

Datapath & Control MIPS

ECE232: Hardware Organization and Design

MIPS processor continued

Vishwani D. Agrawal James J. Danaher Professor

Lecture 9. MIPS Processor Design – Decoding and Execution

MIPS Microarchitecture Multicycle Processor

Basic Building Blocks Multiplexer Demultiplexer Adder +

COMP541 Datapaths I Montek Singh Mar 18, 2010.

The branch instruction

Review Fig 4.15 page 320 / Fig page 322

Basic Building Blocks Multiplexer Demultiplexer Adder +

CS/COE0447 Computer Organization & Assembly Language

The Processor: Datapath & Control.

Computer Organization Lecture 19

CPU Design use pipeline

MIPS Processor.

Processor: Datapath and Control

CS161 – Design and Architecture of Computer Systems

ELEC / Computer Architecture and Design Spring 2015 Pipeline Control and Performance (Chapter 6) Vishwani D. Agrawal James J. Danaher.

CS/COE0447 Computer Organization & Assembly Language

Presentation transcript:

ADITI SHINDE CHIDAMBARAM ALAGAPPAN CPU DESIGN PROJECT ADITI SHINDE CHIDAMBARAM ALAGAPPAN

Features Multicycle Datapath 16 Registers 16 instructions having 4 bit opcode

ISA R -TYPE: I TYPE J-TYPE B-TYPE Opcode (4) Src 1 (4) Src 2(4) Dest (4) Opcode Src (4) Dest(4) Imm val. Opcode (4) Jump Address (12) Opcode(4) Reg1 Reg2 Label

REGISTERS NAME FUNCTION NUMBER $zero Hard wired zero $0 $at Used for pseudo-instructions $1 $ra Return address $2 $s0-$s3 Saved registers $3-$6 $to-$t3 Temporary registers $7-$10 $a0 and $a2 Arguments registers $11-$12 $v0-$v2 Value registers $12-$15

Multicycle Datapath Memory ALU Instr. reg. (IR) PC A Register file PCS PCW 12 to 15 to Control FSM 0-11 RW 8-11 4-7 PC Instr. reg. (IR) A Addr. Memory 0-3 Register file ALU ALUA ALUB AOut ID Data Mem. Data Reg (MDR) B RD IRW 1 Control unit Sign extend MRg -1 MW 12-15

FSM Start State 0 1 Instr. fetch/ adv. PC lw or sw J R B 3 2 Read decode/reg. fetch/branch addr. lw or sw J R B 3 2 Read memory data Compute memory addr. ALU operation Write jump addr. to PC Write PC on branch condition lw 6 8 9 sw 4 5 Write register Write memory data 7 Write register

INSTRUCTION SET 1. Add 2. Sub 3. And 4. Or 5. Nor 6. Slt 7. Lw 8. Sw 9. Addi 10. Andi 11. Beq 12. Jump 13. Jal 14. Jr

PROBLEMS FACED Smaller value of offset (4 bits) Halt – Hardwired -1 Opcode (4) Src (4) Imm.val

PROSPECTIVE CHANGES Micro programmed Control Unit Hardware changes for faster execution Effective programming for preventing latches Reduce critical path delay for accommodating faster execution

QUESTIONS ??