The MDT TDC ASIC Development J. Chapman, T. Dai, Y. Liang, T. Schwarz, J. Wang, X. Xiao, J. Zhu, B. Zhou University of Michigan September 29, 2016

Background: Overview of the MDT-TDC ASIC Why a new TDC IS NEEDED? Previous AMT is no longer available for production Issues found with the AMT chip Ref: https://indico.cern.ch/event/504237/contributions/2138705/ Develop a new TDC ASIC for the MDT phase II upgrade Comparable timing performance (Tubes unchanged) Additional features: Trigger-less mode => faster serial output interface; Latency Reduction; Radiation Tolerance… AMT3 UM-TDC v1.0 Comparison AMT MDT-TDC UM Technology 0.3 μm CMOS Toshbia 0.13 μm CMOS GF # of channels 24 Resolution 0.78 ns 0.78 ns (~200 ps) Dynamic Range 102.4 us Measurement Rising/falling/TOT Double-hit Resolution <10 ns ~10 ns Trigger Mode Trigger buffer Triggerless mode Trigger buffer (if needed)

Architecture of MDT TDC ASIC 320 Mbps 320 Mbps Custom Layout Part TDC Logic Part Timing resolution determines optimal architecture: Multiple clock phases interpolator @ 320 MHz: 4 phases of 320 MHz => 3.125 ns /4 = 0.78 ns LSB Main components: => Generation of multiple clock phases: ePLL (CERN) => Time Digitization: TDC channels (x24) => Time processing/calibration, output serial interface ( TDC logic part) Custom Layout Details on the three parts in following slides…

1: Multiple-Phase Clocks Generation(1) Nomial: ~30 mW *Block diagram from Filip Tavernier, CERN Programmable input clock frequency of 40, 80, 160 or 320 MHz Output clocks of 160 or 320 MHz (x3 copies) Output phase can be programmed with a resolution of 22.5 degree for the 320 MHz output or 11.25 degree for the 160 MHz: equivalent step ~195 ps For 0.78 ns resolution four copies of 160 MHz with 45 degrees shift, using dual clock edges ----------- only three copies available.  two copies of 320 MHz with 90 degrees shift, using dual clock edges

1: Multiple-Phase Clocks Generation(2) Simulated 16 Clock Phases of 320 MHz from ePLL p0 p0 p3 p4 p7 p8 p11 p12 p15 ~ 200 ps

2: Channel Time Interpolator (single TDC channel) φ=0 φ=π/2 φ=π φ=3π/2 φ=π/4 Coarse Time: dual-counter Fine time Interpolator Hit samples clocks! A single channel with Dual edges Time digitization for each edge in a channel => Range :102.4 us + 0.78 ns bin A single Channel: dual edges processed independently Combined in Logic in pair mode. Coarse Time Coarse time + Fine time Total time: 17 bits Dual counters Each works @320 MHz 15 bits to cover 102.4 us 4 phase of 320 MHz One additional Phase 2 bits covering 3.125 ns

2: Channel Time Interpolator (Floorplan towards 24 channels) #4 #7 #8 3x 320 MHz Quad-chnl TDC Quad-chnl TDC Symmetric Layout => Top+ bottom => Both clocks and channels Channels for each half => three quad-chnl TDC building blocks. => Channel outputs directly to “TDC logic” Clocks => ePLL output clocks: 3 copies 320 MHz (the 0, 90 degree are mandatory) #3 Decoupling cap. Quad-chnl TDC TDC logic #0 Clock source: ePLL ePLL Quad-chnl TDC 4 channels Decoupling cap. Quad-chnl TDC Quad-chnl TDC 3x 320 MHz

3: TDC Logic Inputs: => digitized time from all 24 channels: leading/trailing edge, coarse+ fine time => Configuration bits, including calibration data, lookup tables, etc Outputs: two serial lines @160 Mbps/320 Mbps “Chnl Logic” performs all time calibration/correction/noise suppression, etc Chnl Logic FIFO ch 0 Priority Encoder (multiplexer) Build frame Serializer Line 0 Chnl Logic FIFO ch11 Line rate: 320 Mbps or 160 Mbps Mode: debug/nominal working In debug mode, all raw data will be output Chnl Logic FIFO ch12 Priority Encoder (multiplexer) Build frame Serializer Line 1 Chnl Logic FIFO ch23

TDC Performance Analysis φ=0 Bin 1 Bin 2 Bin 3 Bin 4 Meta-stability may occur at clocking edges 45 degree could be added for cross-checking the effect of meta-stability. Setup/hold time induces meta-stability, selection of DFFs with short meta-stability time is important! φ=π/2 “1001” “1100” “0110” “0011” Clock H/L Ratio Matters: Bin width is defined as interval between clock edges: Bin 1: rising edge (0) -> rising edge (pi/2) Bin 2: risng edge (pi/2) -> trailing edge (0) Bin 3: trailing edge (0) -> trailing edge (pi/2) Bin 4: trailing edge (pi/2) -> rising edge (0) φ=π φ=3π/2 φ=π is an inversion copy of φ=0; φ=3π/2 is an inversion copy of φ=π/2 Ideally four fine codes: Meta-stability bits/ambiguous bits corrected from lookup table / 45-deg phase clock Ref: https://indico.cern.ch/event/504237/contributions/2138722/ Bin size is the phase difference of TDC clocks (320 MHz) Nonlinearity arouses from: PLL source, clock tree, TDC channel itself.

TDC Performance Analysis: PLL output clocks + clock trees Bin 1 Bin 2 Bin 3 Bin 4 Proper Choice of the clock tree buffers can suppress the degradation to the minimum Corner: 1.35 V, 125 deg, ss H/L Ratio from ePLL output clocks only Real-time H/L ratio of the ePLL output clocks H/L ratio: 46% Clocks from ePLL tend to have a lower than 50 % H/L ratio. Bin 1/3 not affected, Bin 2 shrunk, Bin 4 expanded Proper Choices of the clock tree buffers can suppress the degradation by clock trees to the minimum: => H/L variation from clock trees is < 0.5 % in this implementation.

TDC Performance Analysis: TDC channel Bin Variation Ideal clocks are used as input for simulation (ePLL not included) Bin size is obtained by sweeping the channel at 7 ps step. Simulation : 1.5V, tt corner, 25 deg Rising edge Chnl #0 Bin Size (ps) Trailing edge Chnl #0 Bins in a Quad-chnl TDC Circuits inside TDC channel will increase H/L ratio Bin 1 and Bin 3 are relatively uniform. Bin 2: expanded Bin 4: shrunk! Bin 2 Bin 4 φ=0 Bin 1 Bin 3 φ=π/2

TDC Performance Analysis: Nonlinearity in together TDC chnl itself equivalent to a H/L ratio >50% for clocks ePLL has < 50% H/L ratio for output clocks Nonlinearity Suppressed? 780 ps Bins in a Quad-chnl TDC

Summary, Current Status & Outlook Project Motivation Design Consideration Performance Analysis Current Status: Design submitted: August 18 Die size: 3.468 x 4.812 mm^2 Packaging preparation in progress (QFN 100) Test board design in progress Outlook: Die expected back in Nov. Tests done by end of this year Combined tests with CSM brds Next prototype: => Full functions considered, including TMR… Collaboration with MPI +USTC => Possible resolution boost-up.

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Meta-stability bits in Simulation CLK Hit Hit is approached to the clock edges at a step of 10 ps q[0-3]: 0011 q[0-3]: 0110 Meta-stability bit detected!

Setup/Hold time Characterization OC_DynamicFF (in GBT-SER Library) Corners 1 Delay of clk & q setup hold ss-125°-1.4V 30 15 20 100~125 tt-25°-1.5V 18 5 13 65~90 ff-(-25°)-1.65V 3 9 47~60 unit:ps Setup+hold: ~ 30 ps DFF in the GF-130 Digital cell lib: cmos8rf DFF_E Corners 320MHZ Clock Check 1 Delay of clk & q setup hold ss-125°-1.4V ok 115 125 230~360 tt-25°-1.5V 58 80 149~204 ff-(-25°)-1.65V 38 52 100~160 DFF_H 105 121 260~430 68 78 170~248 45 50 112~157 DFF_K 117 118 212~368 75 137~218 48 91~165 unit:ps Setup+hold: ~ 120 ps

Correction on Meta-stability bits edge:0 All meta-stability bins can be corrected! edge:3 edge:1 Worst case error is only one fine bin edge:2

Performance Analysis : TDC channel Bin variation Simulation is done by sweeping TDC by an input with a period of 25.007 ns ( 7 ps step). Ideal clocks are used (H/L ratio etc) Contribution from TDC channel only, ePLL not included Bin Size (ps) Zoom in TDC bin (780 ps/bin) simulation corner: ff simulation corner: ss 780 ps Bin Size (ps) TDC bin (780 ps/bin)

Nonlinearity: PLL clocks along clock tree unit: ps Bin 1 Bin 2 Bin 3 Bin 4 input 754.95 699.62 750.79 931.27 # chnl 1 755.01 699.58 751.42 930.67 # chnl 2 754.09 705.78 750.26 926.52 # chnl 3 753.34 712.7 749.2 921.42 # chnl 4 752.56 718.94 748.58 916.71 # chnl 8 752.8 740.09 748.5 894.54 PLL 1st chnl along clk tree 8th chnl along clk tree Corner: 1.35 V, 125 deg, ss Clock tree preserves the nature of PLL output clocks very well A very small ambiguous shows on Bin 2 and 4, about 6 ps/chnl Bin 1 and 3 are stable as they are corresponding to rising-rising, trailing-trailing edges Bin size (ps) Bin 1 Bin 2 Bin 3 Bin 4 Simulation results for more corners are on the way…

Clk320_c1 Clk320_in Clk320_c0 Clk320_out