Two-phase Latch based design For this class I followed a methodology using synopsys tools for the implementation of two phase latch based design. Patricia Gonzalez Department of Electrical Engineering University of Virginia May 09 2014 11/9/2018

Agenda Why ? What ? How ? Results For this presentation I want to make sure I answer the following Wh questions. Why would be choose a Two phase latch based implementation Then What is a two phase latch based implementation Then How we implement it And finally show you some results. 11/9/2018

Why Two-Phase Latch Designs (1) Minimum clock Period Worst case Logic Time Borrowing. Time Slack. To understand why, lets remember that in an edge triggered system the worst case logic path between registers determines the minimum clock period. If a logic block finishes before the end of the clock period, it has to sit idle until the next clock cycle. A Two phase design allow us to utilize this idle time from other stages. 11/9/2018

Why Two-Phase Latch Designs (2) Sub-threshold Systems PVT Variation Impact Then there is the Subthreshold design space that seems promising for all the ultra low power electronics but its yield is dramatically affected by PVT variations. [1]Zhang, Yanqing 11/9/2018

Why Two-Phase Latch Designs (3) Synthesis : buffer insertion. Energy Savings between 37% and 47%. Yield Increase due to post tapeout hold time adjust. Post Tape out adjustment YQ showed in on his papers, that to address PVT variation, the synthesis flow inserts in average 3 or 4 buffers per path with can cause in average a 12% of energy overhead. So a two phase latch design can reduce the need of buffer insertion therefore imply saving energies. Besides there is a yield increase due to post tapeout hold time adjust. 11/9/2018 [1]Zhang, Yanqing

What is Two Phase Latch design 1 This is how a two phase latch based design should look like. We have latches clocked by non overlapping clock1 and clock2 and between each stage of latches we have the combinational logic. So le me pull up a timing diagram. And notice that due to the transparent nature of the latches the Data In has all this time to propagate and be stable so latch2 can grab it. Which is time borrowing. Also, there is the possibility that the data in is stable way 10, then the combnational has all this new time to finish its computation. Which is time slack. This implies a performance improvement. 2 1 2 11/9/2018

How to implement Dual Phase 1. Re-writing the Verilog Edge Triggered Synthesis Latch Based Synthesis 11/9/2018

How to implement dual phase Re-writing the Verilog Disadvantages: Translate all the hdl code. Change test-benches. Re-verify Advantages: Verilog is an exact representation of what we want. Less error during back-end. Latch synthesis techniques. 11/9/2018

How to implement Dual Phase 2. Master Slave Method Requires Master-Slave Cell. Requires minimum verilog modification. 11/9/2018

How to implement Dual Phase Master Slave Method Advantages: Creates a clock tree. Can be inferred from HDL written in edge triggered style. Synthesis version is a good representation of the HDL Minimum hdl modification. Not verification required. Disadvantages It is not what we need. The Master-Slave cell is not available. 11/9/2018

How to implement Dual Phase 3. Modify Netlist Synthesize the edge triggered based design. Optimize for registers. Modify the netlist: Create clocks, wires and Replace every register for two latches. Re - synthesys 11/9/2018

How to implement Dual Phase Modify Netlist Advantages: Quick for proof of concept. Disadvantages No way to ensure that the implementation we end up is actually what we want. More implementation time. Two full synthesis runs. 11/9/2018

How to implement Dual Phase Edge triggered based implementation. Add a second clock as in DFT Synthesize to infer master slave implementation Replace master slave for two latches. Resynthesize How to implement Dual Phase Combination Translate Start from the edge triggered based implementation. Add a second clock to the ports list. Do not connect it to anything. Synthesize to infer Master-Slave implementation. Replace the Master-Slave for two latches. Script. Re-synthesize. Latch based synthesis. 11/9/2018

How to implement Dual Phase Combination Advantages: Creates a clock tree. Can be inferred from HDL written in edge triggered style. Synthesis version is a good representation of the HDL Minimum hdl modification. Not verification required. Fast synthesis for first run. It is just a translation. Test benches are the same. Disadvantages: Still the mapped version is not the same of the hdl model. 11/9/2018

Results MAC FIR 11/9/2018

Case Analysis (MAC) (1) S2, S3 11/9/2018

Case Analysis – MAC (2) 11/9/2018

MAC Unit (1) Results s1 s1 s1 s2 s3 s1 11/9/2018

Simulations Results 11/9/2018

Non combinational Area 3418 1032 Dual Phase Edge Trigered. Nets 1652 1627 Cells 1491 1497 Combinational Cells 1357 1465 Sequential Cells 134 32 Buffers / Inverters 250 264 Combinational Area 12772 13034 Non combinational Area 3418 1032 Net Interconnect 994 825 Total Cell area 16190 14891 11/9/2018

FIR Implementation 11/9/2018

Future Work Power Estimation Logic with Feedback. Leakage Estimation. Full design -> or1200 11/9/2018

References [1]Zhang, Yanqing, and Benton H. Calhoun. "Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method." 11/9/2018