SIDDAGANGA INSTITUTE OF TECHNOLOGY

Slides:



Advertisements
Similar presentations
Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Memory elements. n Basics of sequential machines.
Advertisements

1 On Convergence of Switching Windows Computation in Presence of Crosstalk Noise Pinhong Chen* +, Yuji Kukimoto +, Chin-Chi Teng +, Kurt Keutzer* *Dept.
Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.
NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science FA-STAC.
EELE 461/561 – Digital System Design Module #5 Page 1 EELE 461/561 – Digital System Design Module #5 – Crosstalk Topics 1.Near-End and Far-End Crosstalk.
04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,
מודלים של חיבורי ביניים מודלים חשמליים של חיבורי ביניים עבור מעגלי VLSI פרופ ’ יוסי שחם המחלקה לאלקטרוניקה פיזיקלית, אוניברסיטת ת ” א.
Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.
On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.
NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science Nostra-XTalk.
UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
Signal Integrity Methodology on 300 MHz SoC using ALF libraries and tools Wolfgang Roethig, Ramakrishna Nibhanupudi, Arun Balakrishnan, Gopal Dandu Steven.
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.
Crosstalk Analysis in UDSM technologies
Crosstalk Calculation and SLEM. 2 Crosstalk Calculation Topics  Crosstalk and Impedance  Superposition  Examples  SLEM.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Interconnect design. n Crosstalk. n Power optimization.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 19, 2010 Crosstalk.
Crosstalk Noise Optimization by Post-Layout Transistor Sizing Masanori Hashimoto Masao Takahashi Hidetoshi Onodera Dept. CCE, Kyoto University.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk.
Pipelined and Parallel Computing Partition for 1 Hongtao Du AICIP Research Nov 3, 2005.
-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 21, 2012 Crosstalk.
Copyright © 2009, Intel Corporation. All rights reserved. Power Gate Design Optimization and Analysis with Silicon Correlation Results Yong Lee-Kee, Intel.
High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology
TERMINATIONS Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
1 10 Section 8.1 Recursive Thinking Page 409
Worst Case Crosstalk Noise for Nonswitching Victims in High-Speed Buses Jun Chen and Lei He.
Digital Integrated Circuits A Design Perspective
THE CMOS INVERTER.
REGISTER TRANSFER LANGUAGE (RTL)
VLSI Testing Lecture 5: Logic Simulation
Clocks A clock is a free-running signal with a cycle time.
Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.
5.2 The Integers; Order of Operations
VLSI Testing Lecture 5: Logic Simulation
Introduction Molecules: made up of atoms of individual elements.
M. Martina, G. Masera CERCOM-Dip. Elettronica Politecnico di Torino
Number Theory and the Real Number System
Appendix B The Basics of Logic Design
Week 1 Real Numbers and Their Properties
Synchronous Sequential Circuits
Flip-Flop.
Crosstalk Overview and Modes.
Digital Systems Section 14 Registers. Digital Systems Section 14 Registers.
ECE Digital logic Lecture 16: Synchronous Sequential Logic
SIDDAGANGA INSTITUTE OF TECHNOLOGY
Comparator What is a Comparator?
Chapter 7 Latches, Flip-Flops, and Timers
Satish Pradhan Dnyanasadhana college, Thane
Day 33: November 19, 2014 Crosstalk
ECE 434 Advanced Digital System L12
Limitations of STA, Slew of a waveform, Skew between Signals
How does the CPU work? CPU’s program counter (PC) register has address i of the first instruction Control circuits “fetch” the contents of the location.
Timing Analysis 11/21/2018.
Day 31: November 23, 2011 Crosstalk
Number Theory and the Real Number System
ELEC 7770 Advanced VLSI Design Spring 2010 Interconnects and Crosstalk
Comparator What is a Comparator?
Crosstalk Overview and Modes.
Adding Programmable Delay
332:578 Deep Submicron VLSI Design Lecture 14 Design for Clock Skew
Sequential circuit analysis: kale
Topics Switch networks. Combinational testing..
Submitted by HARSHITHA G H
Week 1 Real Numbers and Their Properties
Short-Term Memory for Figure-Ground Organization in the Visual Cortex
Crosstalk Overview and Modes.
Presentation transcript:

SIDDAGANGA INSTITUTE OF TECHNOLOGY 19/12/16 SIDDAGANGA INSTITUTE OF TECHNOLOGY Seminar on “CROSS TALK DELAY ANALYSIS” PAVITHRA S 2nd Sem M.Tech VLSI Design & Embedded Systems Dept. of E&IE, SIT,Tumkur

CONTENTS: CROSS TALK DELAY AGGRESSOR NET STUDY AGGRESSOR SWITCHING IN SAME DIRECTION AGGRESSOR SWITCHING IN OPPOSITE DIRECTION POSITIVE AND NEGATIVE CROSSTALK ACCUMULATION WITH MULTIPLE AGGRESSORS AGGRESSOR VICTIM TIMING CORRELATION AGGRESSOR VICTIM FUNCTIONAL CORRELATION

CROSS TALK DELAY When a neighboring net is switching, the charging current through the coupling capacitance impacts the timing of the net. Figure below shows net N1 which has a coupling capacitance Cc to a neighboring net (labeled Aggressor) and a capacitance Cg to ground.

Aggressor net steady Net N1 has a rising transition at the output and considers different scenarios depending on whether or not the aggressor net is switching at the same time. The driving cell for the net N1 provides the charge for Cg and Cc to be charged to Vdd. The total charge provided by the driving cell of this net is thus (Cg +Cc) * Vdd.Table shows Base delay calculation- no crosstalk

Aggressor switching in same direction The driving cell is aided by the aggressor switching in the same direction. If the aggressor transitions at the same time with the same slew (identical transition time), the total charge provided by the driving cell is only (Cg * Vdd). If the slew of the aggressor net is faster than that of N1, the actual charge required can be even smaller than (Cg * Vdd). Therefore, the aggressor switching in the same direction results in a smaller delay for the switching net N1.

Aggressor switching in opposite direction The coupling capacitance is charged from -Vdd to Vdd. The charge on coupling capacitance changes by (2 * Cc * Vdd) before and after the transitions. This scenario results in a larger delay for the switching net N1; the increase in delay is labeled as positive crosstalk delay. Table shows Aggressor switching in opposite direction - positive crosstalk.

The reduction in delay is labeled as negative crosstalk delay Table shows Aggressor switching in same direction – negative crosstalk.

Positive and Negative Crosstalk The charge required for the coupling capacitance Cc is larger when the coupled net and victim net are switching in the opposite directions. The aggressor switching in the opposite direction increases the amount of charge required from the driving cell of the victim net and increases the delays for the driving cell and the interconnect for the victim net. When the coupled net and the victim net are switching in the same direction, the charge on Cc remains the same before and after the transitions of the victim and aggressor. This reduces the charge required from the driving cell of the victim net. The delays for the driving cell and the interconnect for the victim net are reduced.

Concurrent switching of victim and aggressor affects the timing of the victim transition. Figure below shows Positive crosstalk delay.

The negative crosstalk affects the timing of the driving cell as well as the interconnect - the delay for both of these is reduced. Figure below shows Negative crosstalk delay. The worst positive and worst negative crosstalk delays are computed separately for rise and fall delays.

Accumulation with Multiple Aggressors The crosstalk delay analysis with multiple aggressors involves accumulating the contributions due to crosstalk for each of the aggressors. When multiple nets switch concurrently, the crosstalk delay effect on the victim gets compounded due to multiple aggressors. Coupling due to multiple aggressors add the incremental contribution fromeach aggressor. Contributions can be added using root-mean-squared (RMS) which is less pessimistic than the straight sum of individual contributions.

Aggressor Victim Timing Correlation The crosstalk can affect the delay of the victim, only if the aggressor can switch at the same time as the victim. The timing windows represent the earliest and the latest switching times during which a net may switch within a clock cycle. If the timing windows of the aggressor and the victim overlap, the crosstalk effect on delay is computed. Possible effect in various timing bins is computed and the timing bin with the worst crosstalk delay impact is considered for delay analysis. The four types of crosstalk delays are positive rise delay (rise edge moves forward in time), negative rise delay(rise edge moves backward in time), positive fall delay and negative fall delay.

The aggressor nets (A1, A2, A3) are capacitively coupled to the victim net (V) and also their timing windows overlap with that of the victim. Figure below shows the timing windows and the possible crosstalk delay impact caused by each aggressor

In this example, the timing window overlap region is divided into three bins - each bin shows the possible aggressors switching. Bin 1 has A1 and A2 switching which can result in crosstalk delay impact of 0.26 (= 0.12+ 0.14). Bin 2 has A1 switching which can result in crosstalk delay impact of 0.14. Bin 3 has A3 switching which can result in crosstalk delay impact of 0.23. A net can be coupled to aggressors A1, A2, A3 andA4. During crosstalk delay analysis, it is possible that A1, A2, A4 contribute to positive rise and negative fall delay contributions whereas A2 and A3 contribute to negative rise and positive fall delay contributions.

Aggressor Victim Functional Correlation Timing windows, crosstalk delay calculation can consider the functional correlation between various signals. The scan control signals only switch during the scan mode and are steady during functional or mission mode of the design. The scan control signals can not be aggressors during the functional mode. The scan control signals can only be aggressors during the scan mode in which case these signals can not be combined with the other functional signals for worst-case noise computation.

Another example of functional correlation is a scenario where two aggressors are complements of each other. For such cases, both signal and its complement can never be switching in the same direction for crosstalk noise computation. This type of functional correlation information, when available, can be utilized so that the crosstalk analysis results are not pessimistic by ensuring that only the signals which can actually switch together are included as aggressors.

THANK YOU