Data Hazards and Stalls

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Data Hazards and Stalls Data hazards and forwarding Data Hazards and Stalls 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

An Example Assuming that register R2 = 10 initially. And the sub instruction will result in R2 = -20. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Pipelined dependencies in a five instruction sequence using simplified datapaths to show the dependencies. Note: only add and sw get the right value R2 = - 20 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

An Example (cont’d) Hazard condition (between sub and and at the indicated stages): EX/MEM.RegisterRd = ID/EX.RegisterRs = $2 General 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt Question: can you identify which of the 4 conditions Here captures the hazards condition between sub and or ? 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Forwarding/Bypassing ALUinputs can also from pipeline registers Extra multiplexors Hazard detection units 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

The dependencies between the pipeline registers move forward in time, so it is possible to supply the inputs to the ALU needed by the and instruction and or instruction by forwarding the results found in the pipeline registers rather than stall. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

the ALU and pipeline register before adding forwarding. a. No forwarding the ALU and pipeline register before adding forwarding. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Forwarding control and the multiplexors are added b. With forwarding Forwarding control and the multiplexors are added 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

The control values for the forwarding multiplexors. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Forwarding Conditions 1. EX hazard: if(EX/MEM.RegWrite and (EX/MEM.RegisterRd =/= 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

and (MEM/WB.RegisterRd =/= 0) Con’d 2. MEM hazard: if(MEM/WB.RegWrite and (MEM/WB.RegisterRd =/= 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Priority in Forwarding Add $1, $1, $2 Add $1, $1, $3 Add $1, $1, $4 …. Note: here both EX and MEM stages may have the exact hazard conditions. What should we do ? 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Priority in Forwarding If (MEM/WB.RegWrite and (MEM/WB.RegisterRd =/= 0) and (EX/MEM.RegisterRd =/= ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) Forward A = 01 if (MEM/WB.RegWrite and (EX/MEM.RegisterRd =/= ID/EX.RegisterRt) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Note: When both EX and MEM stages may have the exact hazard conditions. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

The datapath modified to resolve hazards via forwarding. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

The Snapshots of Our Example Through Forwarding 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 3 of the instruction sequence. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 4 of the instruction sequence. add $9, $4, $2 or $4, $4, $2 and $4, $2, $5 sub $2…… before <1> Clock cycles 4 of the instruction sequence. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 5 of the instruction sequence. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 6 of the instruction sequence. after <2> after <1> add $9, $4, $2 or $4…… and $4…... Clock cycles 6 of the instruction sequence. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Hazards and Stalls 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

A pipelined sequence of instructions. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

The way stalls are really inserted into the pipeline. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Forwarding with Load and Stores The problem The solution 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

A Hazard Detection Unit In the ID stage, the following should be checked by the hazard detection unit, so it can insert the stall between a load and its use. if (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) stall the pipeline 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Pipelined control overview, showing the two multiplexors for forwarding, the hazard detection unit, and the forwarding unit. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

“Snapshots” of the running example through the pipeline 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 2 of the instruction sequence in the example. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 3 of the instruction sequence in the example. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 4 the instruction sequence in the example. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 5 of the instruction sequence in the example. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 6 of the instruction sequence in the example. 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Clock cycles 7 of the instruction sequence in the example. (note the forwarding of r4) 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

Branch Hazards and Handling Branch hazard handling methods Static Dynamic 2018/11/10 \course\cpeg323-05F\Topic6c-323.ppt

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