MIPS processor continued

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Presentation transcript:

MIPS processor continued

Review Different parts in the processor should be connected appropriately to be able to carry out the functions. Connections depending on what we need Learnt R-type, lw, sw, beq

In Class Exercise Question Design a simplified MIPS processor that supports only addi. Assume the control signals have been generated and only the data path needs to be designed. addi $rt, $rs, imm opcode (6 bits) rs (5 bits) rt (5 bits) imm (16 bits)

In Class Exercise Answer Design a simplified MIPS processor that supports only addi. Assume the control signals have been generated and only the data path needs to be designed. addi $rt, $rs, imm opcode (6 bits) rs (5 bits) rt (5 bits) imm (16 bits) 26:21 20:16 15:0

lw & sw? Do both lw and sw, and ask for student participation

Data path only for lw and sw (answer) To support two instructions, first just get one done, then see if it still works for the second. If it works then done. Otherwise, see what wires need to be added.

Data path for both R-type and memory-type instructions add $rd, $rs, $rt, format: opcode (6 bits) rs (5 bits) rt (5 bits) rd (5 bits) 00000 funct (6 bits) lw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits) sw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits) Some connecttions are the same, like readreg1, ALUa Sometimes wreg is this, sometimes that Sometimes ALUb is readdata2 (add), sometimes it is the immediate number (lw, sw) Sometimes Wdata is this, …

Data path for both R-type and memory-type instructions add $rd, $rs, $rt, format: opcode (6 bits) rs (5 bits) rt (5 bits) rd (5 bits) 00000 funct (6 bits) lw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits) sw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)

Answer

Datapath for R-type, memory, and branch operations

Datapath for R-type, memory, and branch operations (Answer)

Datapath for Memory, R-type and Branch Instructions, plus the control signals

Jump Instruction Jump instruction seems easy to implement We just need to replace the lower 28 bits of the PC with the lower 26 bits of the instruction shifted by 2 bits The shift is achieved by simply concatenating 00 to the jump offset 11/15/2007 5:02:11 PM week-13-3.ppt

Implementing Jumps The one we have supports arithmetic/logic instructions, branch instructions, load and store instructions We need also to support the jump instruction What are the changes we need to make? 1 31 opcode Address 26 25

Add j?

Supporting Jump Instruction

In Class Exercise 11/25/2007 10:54:43 PM week-14-1.ppt