EMC-Aware System Design - A focus on Integrated Circuits Etienne SICARD Professor etienne.sicard@insa-toulouse.fr www.ic-emc.org INSA TOULOUSE - FRANCE

TOULOUSE, FRANCE Airbus A380 Founded in -120 B.C Cassoulet Best place to study in France (2015 ranking) (heavy responsibility) Airbus A380 Cassoulet Rugby

CONTENTS General context Integrated Circuits Electromagnetic Compatibility Design Guidelines

1 GENERAL TRENDS

Electronic Market Growth Share of system sales 2020 vs 2015 VISION 2020 Increasing disposable income, Expanding urban population, Growing internet penetration and Availability of strong distribution network Smartphones PC TV Automotive Internet of Things Tablets Game consoles Medical Servers -10% Growth 10% 20% Electronic Market Growth

MOBILE BUSINESS https://www.gsmaintelligence.com/ 4G 3G 2G http://www.ericsson.com/ericsson-mobility-report

INTERNET OF THINGS Growth in 2016 was stalling (+5% smarthones) Consumer demand was sluggish (tablets, laptops). Demand for Internet of Things (IoT) wasn't growing fast enough to offset declines Price, security and ease-of-use remain barriers to the adoption of new IoT devices and services.

TOWARDS AUTOMATIC DRIVE ADAS TOWARDS AUTOMATIC DRIVE 2020 : Injury-free driving 2030: Accident-free driving ? 2040: Autonomous driving?

2 TECHNOLOGY TRENDS

SCALE DOWN BENEFITS 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm Smaller Faster Less power consumption Cheaper (if you fabricate millions) Room for other devices Processors Memory Security Sensors 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm

MOBILE COMMUNICATIONS Technology 130nm 90nm 45nm 28nm 14nm 5nm Complexity 100M 250M 500M 2G 7G 150 G Packaging Mobile generation 3G+ 4G 4G+ 5G 3G 2004 2007 2010 2013 2016 2020 Core+ DSP 1 Mb Mem Core DSPs 10 Mb Mem Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors ? Embedded blocks

GOING ATOMIC SCALE Si lattice: 0.23 nm 14-nm Xeon by Intel ™ IBM, GlobalFoundries, Samsung, SUNY first 7-nm testchip 2017 Qualcomm™ Snapdragon X50 Si lattice: 0.23 nm

Stacked process layers GOING 3D - MEMORIES Stacked process layers 8, 16, 32 layers of active devices 1 tera-bit/cm2 achieved 5 years ahead from roadmaps

High Bandwidth Memory (HBM) Hybrid Memory Cube (HMC) 3D IC TECHNOLOGY High Bandwidth Memory (HBM) Hybrid Memory Cube (HMC) http://www.eejournal.com/article/20170102-hbm-hmc/ November 18

GOING 3D – Package on Package Upper MEM SoC to PCB MEM to SoC (TMV) MEM to PCB (TMV) PCB PCB Bottom SoC E. Sicard, EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package, EMC Compo 2015 Edinburgh

GOING 3D – Stacked Dies Processor die THERE IS PLENTY OF SPACE ON THE TOP 3D technology uses stacked dies, through-silicon-vias Enables 10-20 Gb/s/pin at 1.0V Samsung 3D (Galaxy 6) vs PoP (Galaxy 5) : 30% faster 20% less power Less heat Thinned memory die 10 µm Multicore 350 µm thickness Direct bond interconnect (DBI) Package leadframe (GND) Through Silicon Via (TSV) Possible 3rd die Bottom die Upper die http://www.youtube.com/watch?v=Rw9fpsigCfk

3 ELECTROMAGNETIC COMPATIBILITY

ONE ACRONYM – TWO PROBLEMS SUSCEPTIBILITY TO INTERFERENCE EMISSION OF PARASITIC NOISE Personal Devices Safety systems interferences Carbon airplane Equipment Boards Susceptibility to radio frequency interference is illustrate in the case of a very high radar wave illuminating an airplane. This situation is very common at the proximity of airports. A Giga-watt pulse is received by the the plane, which captures some energy which may flow to the equipment, the board and finally to the component. On the other hand, the parasitic emission due to the integrated circuit inside a car may jeopardize the correct behavior of personal devices such as mobile phones, and RF links. In some case, the parasitic energy may be high enough to parasite the safety systems of the car. Radar Components Hardware fault Software failure Function Loss

SUPPLY VOLTAGE SCALE DOWN Less noise margin (<100 mV in 7-nm) 10-nm technology Supply (V) 5.0 0.7 V inside, 1.2V outside 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node

HIGHER FREQUENCIES 2,3,4,5G mobile frequencies 1 GHz 2 GHz 3 GHz 800 2-3G 900 2-4G 1800 3G 1900 4G 2600 Today 5G 700 1 GHz 2 GHz 3 GHz Tomorrow 5G 3300 5G 4400 5G 26 250 5G 42 500 10 GHz 20 GHz 30 GHz 40 GHz

Data Rate per pin (Gb/s) MORE I/O NOISE I/O Technology Multi-Giga-Bit link between processors & memories : video, object recogn., 3D capture Generation 4x and 5 on the market Generation 6 under development DDR4x: 230 ps, 0.25 V swing Data Rate per pin (Gb/s) 100 Gb/s Graphics trends GDDR6 GDDR5 Low power trends GDDR4 10 Gb/s GDDR3 LP5 LP4x GDDR2 LP4 LP3 LP2 DDR5 DDR4x DDR4 DDR trends DDR2 DDR3 1 Gb/s 2010 2012 2014 2016 2018 2020

Technology WIDE RANGE OF OPERATING VOLTAGES Nano-CMOS operates below 1V, noise margin around 50 mV Close to medium voltage (12, 24, 48 V) and high voltage (98, 240, 300, 400, 850 V) functions ADC with 16-24 bit resolution work at 10-100 µV resolution

4 DESIGN GUIDELINES

MOTIVATION Use tools, guidelines and trainings in EMC of Integrated circuits, for improved EMC before fabrication Design Guidelines Tools Training DESIGN Architectural Design Design Entry Design Architect EMC Simulations Compliance ? GO NO GO Simulation approaches for Electromagnetic Compatibility (EMC) evaluation have become critical to shorten design cycles of modern integrated circuits (IC). Including reduction techniques in the early design phases and simulating the parasitic emission or susceptibility to EMI before fabrication requires efficient IC models, adequate tools and EMC aware engineers. Models related to EMC start appearing, as well as specific tools to handle the EMC behaviour of the IC.However, the knowledge on EMC at component level is still a matter of a few experts. Real-case measurements and models are mostly confidential, which jeopardize the share of general knowledge on this topic. Moreover, EMC education in university or industry requires not only formal courses based on specific books, but also trainings based on real cases. In order to provide a unique tool only dedicated to the simulation of emission and susceptibility prediction at integrated circuit level and a training tool, we have developed IC-EMC The aim of this presentation is to detail philosophy of this tool and the main simulation features of IC-EMC. FABRICATION EMC compliant

Memory PLL Digital core Current density simulation Layout view DESIGN GUIDELINES - SUPPLY Place supply pairs close to noisy blocks Layout view Current density simulation Memory PLL Digital core VDD / VSS The good solution consists in the placement of VDD/VSS pad pairs. VDD/VSS rails should also be routed as close as possible. This increases decoupling capacitance. Also, multiple pairs significantly reduce the internal loops.

9 I/O ports DESIGN GUIDELINES - IOS Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs 9 I/O ports It reduces serial inductance  SSN. It reduces also inductive crosstalk between signal traces since supply pairs conducts returning signal current. A good ratio for number of supply pairs on number of IO is about 8.

DESIGN GUIDELINES – CANCEL FIELDS Radiated field Reduced field Reduce current loops that provoke magnetic field Added contributions currents Die Lead current EM wave Reduced contributions The second important rule consists is placing VDD and VSS supply as close as possible from each others. This reduces the surface of the current loop which provokes immediate parasitic emission, in radiated mode. A very bad pin assignment consists in one VDD supply on one side, one VSS supply on the other side. This lead to a maximum emitted parasitic energy. Consequently, the current wires placed together almost cancel the magnetic field and significantly reduce the radiated signature of the IC. Gains higher than 20dB have been observed in TEM cell measurements.

DESIGN GUIDELINES – REDUCE SWITCHING NOISE Reduction of clock buffer’s drive Spread of the switching 20dB noise reduction Reduce drive, limit slew rate, Adapt impedance, Add local decoupling 20dB noise reduction J-P. Leca “Microcontrollers Electromagnetic Interferences Modeling and Reduction”, PhD report, Univ of Nice, France, 2012

DESIGN GUIDELINES – ISOLATE AND DECOUPLE On-chip decoupling Resistive supply path Substrate isolation Separate supply Separation between incompatible blocks Immunity level (dBm) Decoupling capacitance Separate supply substrate isolation Substrate isolation No rules to reduce susceptibility Frequency Work done at Eseo France (Ali ALAELDINE)

DESIGN GUIDELINES - SHIELDING Thin magnetic-nonmagnetic multi-layered structure Trench-via array and multi-layered conductor structures (5G, 28-39 GHz) http://prc.gatech.edu/hg/item/585164 Graphene in stacked dies 10-15dB coupling reduction K. Kim, “Graphene-based EMI Shielding for Vertical Noise Coupling Reduction in 3D Mixed-Signal System”, 2012

CONCLUSION

CONCLUSION www.ic-emc.org The electronic market growth should be driven by 5G mobile, automatic drive, Internet of Things, etc. The trends towards nano-CMOS have been illustrated EMC concerns in terms of noise margin, higher frequencies and IO bandwidth Design guidelines for improved EMC have been introduced www.ic-emc.org

Thank you for your attention Special thanks to Prof Thank you for your attention Special thanks to Prof. Norocel CODREANU, CETTI