A. Mishchenko S. Chatterjee1 R. Brayton UC Berkeley and Intel1

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Presentation transcript:

A. Mishchenko S. Chatterjee1 R. Brayton UC Berkeley and Intel1 Boolean Factoring and Decomposition of Logic Networks A. Mishchenko S. Chatterjee1 R. Brayton UC Berkeley and Intel1

Outline Introduction Disjoint Support Decomposition (DSD) Non-disjoint decompositions Common Boolean divisors Application to LUT mapped networks Experimental results Conclusions

Introduction Factoring and decomposition are done traditionally by algebraic methods These are fast but limited in many ways Boolean methods look at a logic equation as a logic function rather than a given structure Ashenhurst-Curtis is an example of a Boolean decomposition method. How to find Boolean decompositions or common Boolean divisors in a fast way?

Disjoint Support Decomposition (DSD) (Simple Disjunctive Decomposition) Theorem 1 [Ashenhurst 1959]. For a completely specified Boolean function, there is a unique maximal DSD (up to the complementation of inputs and outputs and factoring of ANDs/ORs and XORs). E C D A B G x1 x2 x3 x4 x5 H F D a c 1

Basic Inner Core Algorithm (DSD) We use a fast DSD algorithm as our underlying subroutine It is basically that of Bertacco and Damiani. "The disjunctive decomposition of logic functions". ICCAD '97, but use heuristics to speed it up use truth tables limit inputs to up to 16. BDD

Non-disjoint decomposition Definition: A function F has an ( ) -decomposition if it can be written as where ( ) is a partition of the variables x and D is a single output function. H D a c b The variables in the set b are called the shared variables. The variables a are called the bound set and c the free set. 1

Example (non-disjoint) Has an ({x2,x3,x4},{x1}) decomposition F(x1,x2.x3,x4,x5,x6) x1 1 F(x1,x2.x3,x4,x5,x6) 1 x1 1 D x1 1 x5 x6 x2 1 1 x2 1 x3 x4 x5 x6 x2 x3 x4 Might prefer the one on the right because it can be mapped into two 4-LUTS whereas the left one requires three 4-LUTS.

Non-disjoint decomposition Theorem 2: A function F(a,b,c) has an (a,b)-decomposition if and only if each of the b cofactors of F has a DSD structure in which the variables a are in a separate block. For the cofactors are E C D A B G x4 x5 x1 x2 x3 X Z W Y x4 x5 x1 x2

Common Divisors Theorem 3. There exists a common (a,b)-divisor of {F1, F2} if and only if F1 is (a,b)-compatible with F2. H2 D a c2 b H1 c1

Application of Factoring (uses Theorem 2) Rewriting a K-LUT mapped circuit. For each LUT, and each cut of no more than 16 inputs, express the output of the LUT in terms of the cut variables – F(x) Find variables b such that its cofactors are support reducing (we look for up to two variables in the b set) Take the best (a,b) set and and decompose F=H(D(a,b),b,c) Recursively decompose H and D if they do not fit into LUT. If improvement, replace LUTs in cut with its new decomposition.

Example (non-disjoint) F(x1,x2.x3,x4,x5,x6) x1 1 H F(x1,x2.x3,x4,x5,x6) 1 x1 1 D x1 1 x5 x6 x2 1 1 x2 1 x3 x4 x5 x6 x2 D Has an ({x2,x3,x4},{x1}) decomposition x3 x4

Experimental Results Refactoring 6-LUT mapped circuits Objective: Area minimization while preserving delay Scripts: “Baseline” = (resyn; resyn2; fpga_map) “Choices” = Baseline; (choice; fpga_map)4. “Imfs” = Baseline; (choice; fpga_map; imfs)4. “Imfs+Lutpack” = Imfs; (lutpack)2

PI PO Reg Baseline Choice Imfs Imfs + Lutpack alu4 14 8 821 6 785 5 Designs PI PO Reg Baseline Choice Imfs Imfs + Lutpack LUTs Levels alu4 14 8 821 6 785 5 558 453 apex2 39 3 992 866 806 787 apex4 9 19 838 853 800 732 clma 383 82 33 3323 10 2715 1277 1222 des 256 245 794 512 483 4 480 diffeq 64 377 659 7 632 636 634 ex1010 2847 2967 1282 1059 ex5p 63 599 669 118 108 elliptic 131 114 1122 1773 1824 1820 1819 frisc 20 116 886 1748 13 1671 12 1692 1683 i10 257 224 589 560 548 547 pdc 16 40 2327 2500 194 171 misex3 664 517 446 s38417 28 106 1636 2684 2674 2621 2592 s38584 278 1452 2697 2647 2620 2601 seq 41 35 931 756 682 645 spla 46 1913 1828 289 263 tseng 52 122 385 647 649 Ratio1 1.000 0.945 0.919 0.613 0.852 0.580 Ratio3 0.946

Conclusions Presented a fast method for Boolean factoring Applied this to rewriting a LUT mapped network Resulted in 5% decrease in LUT count without affecting delay Method for finding common Boolean factors presented in paper but not implemented yet.