EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #6: Modular Combinational Logic (Thanks to Dr. Perry for the slides) 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Note to Self There are still way too many slides in this module! Need to keep working on making it shorter and more concise 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Wednesday, October 10, 2006 Administrivia: This week’s lab: Finish “Top secret code display” (w. K-maps), finish project Design project #1: Due this Friday!! Test your designs during a lab period, or in TA office hours Don’t delay writing the large required amount of documentation! Homework assignment #3: Due next Monday (October 16th) Plan for today: Show Ping-Pong videogame example, in progress See module #99, Designs (v.3+) for slides Start next lecture topic: Modular Combinational Logic 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Modular Combinational Logic Original slides by Dr. Reginald Perry With modifications & additions by Mike Frank 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Decoders General form: n-to-2n decoder n inputs, 2n outputs For each input pattern, one and only one output line will be active. Uses: “Minterm generator” Bit/word-line (memory access) circuit Code conversion Demultiplexing (routing) of data 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 1-to-2 Decoder Truth table shown at right This one can be implemented by just a simple fan-out and an inverter: x y0 y1 1 y0 y0 x x y1 y1 Circuit schematic Icon 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Recursive Contruction of n-to-2n Decoder out of 1-to-2 and (n−1)-to-2n−1 Decoders w0 …plus 2n AND gates w1 w2 xn−1..0 xn−1..1 2n−1 2n−1 AND gates … n−1 2n 2n−1 AND gates z0 x0 z1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

1-to-2, 2-to-4 and 3-to-8 Decoders using recursive design style in Quartus This is really 4 AND gates in parallel This is really 8 AND gates in parallel 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 add a slide on the other recursive composition of 2k-to-(2^(2k)) decoders 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder – Truth Table X1 X0 Y0 Y1 Y2 Y3 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2 to 4 Decoder Equations 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2 to 4 Decoder: Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder: Block Symbol Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

3 to 8 Decoder – Truth Table x2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 3 to 8 Decoder Equations 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 3 to 8 Decoder: Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

3 to 8 Decoder: Block Symbol Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Design Example Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution m2 m4 m5 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2 to 4 Decoder with Enable 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2x4 Decoder with Enable Enable is abbreviated as EN EN is called a Control Signal Control Signals can be Active High Signal EN = 1 – Turns “ON” Decoder Active Low Signal EN=0 – Turns “ON” Decoder 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 x 4 Decoder with Active High Enable – Truth Table y3 y2 y1 y0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder with Enable Equations 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder with Enable Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder with Enable Symbol 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation) En x1 x0 y3 y2 y1 y0 d 1 d = don’t care En has “highest” priority. If En=0, we “don’t care” about x1 or x0 because Y=0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation) EnL x1 x0 y3 y2 y1 y0 1 d d = don’t care En has “highest” priority. If En=1, we “don’t care” about x1 or x0 because Y=0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2 to 4 Decoder with Active Low Enable Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Design Example Design a 3x8 decoder using only 2x4 decoders and NOT gates. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution “On” when A=0 “On” when A=1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Encoders Opposite of a decoder 2n to n encoder 2n inputs n outputs For each input, the circuit will produce an “encoded” output 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Example: 4 to 2 Binary Encoder Truth Table 1 Assume only one input high at a time!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 4 to 2 Encoder Equations 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Problems with initial design Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1? A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Problems with initial design If IA = 1 => all lines are 0 If IA = 0 => at least one line is 1 Q: What happens if more than one input is high at the same time? A: Design a “priority” encoder that will encode the input with the highest priority. Let’s set X3 with the highest priority, followed by X2, X1, and X0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Example: 4 to 2 Priority Binary Encoder Truth Table 1 d 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y1 Y0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

4 to 2 Priority Encoder Equations 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Monday, October 16, 2006 Administrivia: This week’s lab: “Electronic Device Test” – PO(2/b), experiment Design projects are being graded this week Homework assignment #3 is due tonight Plan for today: Finish current topic: Modular Combinational Logic – MUXes, ALUs 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Multiplexer/Data Selectors MUX Very Important Module!!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Multiplexer(MUX)/Data Selector N to 1 multiplexer (or multiplexor) N=2k data input lines, D0..(N−1) k=log2(N) control inputs, S(k−1)..0 Binary encoding of index of selected data One output: This circuit will “connect” just the selected input to the output. The selected input is specified by decoding the control inputs. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

The Simplest Multiplexer 2-to-1 multiplexer truth table Output is a copy of D0 if S0=0 D1 if S0=1 D0 D1 S0 F d 1 Schematic, using 1-to-2 Decoder module example 2-to-1 MUX Icon 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

General Construction of a 2k-to-1 MUX from a k-to-2k decoder, ANDs, and an OR This is just a direct generalization of the schematic on the previous slide. F “bussed” OR gate 2k 2k 2k This means 2k AND gates in parallel k S(k−1)..0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Recursive Construction of 2k-to-1 mux from two 2k−1-to-1 muxes (& a 2-to-1 mux) 2k−1 k−1 F 2k 2k−1 Sk−1 S(k−2)..0 k−1 S(k−1)..0 k 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

4-to-1 MUX from three 2-to-1 MUXes Try building some larger sizes for yourself… 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Example: 4 to 1 MUX Truth Table Control Inputs Output Data Inputs D0 D1 D2 D3 S1 S0 F d 1 d = don’t care / Di = data on input i 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 4 to 1 MUX Equation D’s are the DATA inputs, AB are control inputs and called the “select” lines. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 4 to 1 MUX Circuit Control Inputs Data Inputs Output 2x4 Decoder Only a single AND gate will be “ON” at a time. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

4 to 1 MUX Symbol Data Inputs Output Control Inputs A more common, and more mnemonic MUX symbol: D0 Data Inputs D1 F Output D2 Control Inputs S1..0 D3 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Logic with multiplexers You can implement any n-input logic function with a single 2n-to-1 multiplexer, by feeding appropriate constants into the MUX’s data inputs. Namely, the list of the function’s output values from its truth table The multiplexer implements a “lookup table” it simply looks up the function result from the indicated row of the truth table Of course, this is generally not the most hardware-efficient way to implement a given function. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

MUX Application Example Using a 4x1 MUX, design a logic circuit which implements: We have, Y 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example Using a 4x1 MUX, design a logic circuit which implements: a b Y Dn D0 1 D1 D2 D3 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Multi-bit Multiplexers J-bit nx1 mux d0 d1 J bits deep d2 F J bits deep … dn-1 sel log2n j=0 to 3 This is just J separate nx1 multiplexers 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4-bit 4x1 MUX D0[3..0] D0[3..0] D1[3..0] D1[3..0] F[3..0] D2[3..0] F[3..0] 4 bits deep D2[3..0] D3[3..0] D3[3..0] A B A B j=0 to 3 This is just 4 separate 4x1 muxes 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4-bit 4x1 MUX Bit 0 Bit 1 Bit 2 Bit 3 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX For the jth output, we have D0[j] D1[j] D2[j] F[j] D3[j] A B 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX For the bit 0 output, we have D0[0] D1[0] D2[0] F[0] D3[0] A B 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX For the bit 1 output, we have D0[1] D1[1] D2[1] F[1] D3[1] A B 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX For the bit 2 output, we have D0[2] D1[2] D2[2] F[2] D3[2] A B 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX For the bit 3 output, we have D0[3] D1[3] D2[3] F[3] D3[3] A B 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 Mux Complete Circuit Bit 0 F[0] Bit 1 F[1] F[2] Bit 2 F[3] Bit 3 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example 4 bit 4x1 MUX Symbol 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Design Example Using a 4bit 4x1 MUX, design a 8bit 4x1 MUX 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

DeMultiplexers/ Data Distributors 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Demultiplexer/Data Distributor Opposite of a multiplexer 1 to N demultiplexer 1 data input N data outputs Log2(n) control inputs This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Example: 1 to 4 DeMUX Truth Table F0 F1 F2 F3 1 d = don’t care / Di = data on input i 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 1 to 4 DeMUX Equations D is the DATA inputs, AB are control inputs and called the “select” lines. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 1 to 4 DEMUX Circuit Only one F will be active 2x4 Decoder Only 1 AND gate will be “ON” 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 1 to 4 DEMUX Symbol Selected Lines Outputs Data Input 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example Design a 3x8 decoder using only 2x4 decoders and NOT gates. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution “On” when A=0 “On” when A=1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Basic Arithmetic Elements Half Adder 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Half Adder-Truth Table S=A+B (arithmetic sum) A B S1 S0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Half Adder Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Full Adder-Truth Table S=A+B+C (arithmetic sum) A B C S1 S0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Full Adder You can show!!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Synthesis Logic Equation Logic Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Synthesis Logic Equation Logic Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Synthesis Full Adder Circuit B S(0) C S(1) S(0) S(1) Simulation 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Full Adder from Two Half Adders Given bits a,b,c, computes (s1s0)2 = a + b + c. Can build it using two half adders to compute the low-order bit of the sum as s0 = (a⊕b)⊕c. Plus an extra OR gate needed to combine the carries. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Ripple Carry Adder 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Conceptualization 4-bit adder (worst case) 1 1 1 1111 11110 For the “worst case” we need to add three bits to generate a single output bit with a possible carry out. Can we use our single bit adder for this? 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Ripple Carry Adder We can cascade several full adders to create a ripple carry adder The circuit gets its name because the carry bit “ripples” from one bit position to the next 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Conceptualization First, let’s look at two bits A(1) FullAdder C A B S(0) S(1) B(1) Sum(1) A(0) FullAdder C A B S(0) S(1) B(0) Sum(0) What about the carry? 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Conceptualization Let’s connect the two full adders A(1) FullAdder C A B S(0) S(1) B(1) S(1) Cin A(0) Cout FullAdder C A B S(0) S(1) B(0) S(0) Set carry in for first bit to 0. Why? 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Analysis Let’s test this for a few cases: FullAdder C A B S(0) S(1) 00 000 FullAdder C A B S(0) S(1) Correct!!! Rule of thumb: Always test simple cases first!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Analysis Let’s test this for the a few cases 1 1 FullAdder C A B S(0) S(1) 1 1 11 110 1 1 FullAdder C A B S(0) S(1) Correct!!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Analysis Let’s test this for the a few cases FullAdder C A B S(0) S(1) 1 1 01 010 1 1 FullAdder C A B S(0) S(1) 1 Correct!!! 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Four Bit “Ripple” Adder Carry out Carry in 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

8-bit Ripple Carry Adder Use two 4-bit adders 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

16-bit Ripple Carry Adder Use two 8-bit adders 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Subtraction Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Subtraction Circuit Calculate 2’s complement of B Add –B to A 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Add/Sub Circuit Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Add/Sub Module Functional Result S=A+B 1 S=A-B Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1. 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Design using Modules 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Add operation. Add=0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Sub operation. Add=1 1 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Wednesday, October 18, 2006 Administrivia: This week’s lab: “Electronic Device Test” – PO(2/b), experiment Next week’s lab: Midterm Practical Exam Design projects are being graded this week Homework assignment #4 will be out soon! Plan for today: Finish current topic: Modular Combinational Logic – Comparators, ALUs 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Comparators 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Equal Comparator Design a logic circuit which will compute F0 = (A = B) 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Equal Comparator Truth Table F0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Equal Comparator Truth Table F0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution You can show, 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

N-bit Equal Comparator 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Not Equal Comparator Design a logic circuit which will compute F = (A <> B) F = (A = B) i.e. Just invert our Equal Comparator circuit 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Magnitude Comparator Design a logic circuit which will compute F2 = (A>B) F1 = (A<B) Let’s develop a truth table for 2-bits 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Magnitude (unsigned) Comparator Truth Table F2 F1 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Magnitude (unsigned) Comparator Truth Table F2 F1 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 You can show 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Logic Units (ALUs) 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Logic Unit (ALU) A,B are data inputs of n bits each in depth S is a control input. We have 2m operations F is the output 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example Let n=4,m=3 We have A[3..0] and B[3..0] With m=3, we have 23 = 8 operations Let’s look at a possible function table 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Function Table s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Design using a Truth Table How large is the truth table? 2n from data inputs A and B Example: n=8, we have 16 data inputs A[7..0] and B[7..0] 3 control inputs Total of 2n+3 inputs N=8, we have 19 inputs Our truth table will have 192 (361) rows and 8 outputs Too complex. Let’s explore another alternative using a “system” or modular approach 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Design using Modules Note: For S2=0, we have logic operations For S2=1, we have arithmetic operations So, let’s use S2 to control a 2x1 MUX to select between logic and arithmetic operations, so our top level design would look like: 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design S2=0 With S2=0, F is the output from the logic module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design S2=1 With S2=1, F is the output from the arithmetic module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Logic Module S2=0 s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B We can use a 4x1 mux to implement this module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=AB AND Operation S[1..0]=00 0 0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A+B OR Operation S[1..0]=01 0 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A NOT Operation S[1..0]=10 1 0 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A XOR B XOR Operation S[1..0]=11 1 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

What do these logic modules look like? 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 AND Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 OR Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 NOT Module A F 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 XOR Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Let’s use our ADD/SUB Module Arithmetic Module Let’s use our ADD/SUB Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Add/Sub Circuit Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Arithmetic Ops 1 F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1 Note: S0 can be use to indicate Addition or Subtraction. S1 can be use to indicate the B data input 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A+B S[1..0]=00 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A-B S[1..0]=01 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A+1 S[1..0]=10 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A-1 S[1..0]=11 1 1 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Overall Design We have 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Total Design Logic Module Arithmetic Module 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 End of Chapter 4 11/11/2018 M. Frank, EEL3705 Digital Logic, Fall 2006