Chapter 5 Transistor Bias Circuits

Objectives Discuss the concept of dc bias in a linear amplifier Analyze voltage-divider bias, base bias, emitter feedback bias and collector-feedback bias circuits. Basic troubleshooting for transistor bias circuits

5.1 The DC Operating Point In order to operate the transistor in a linear amplifier, a transistor must be properly biased with a dc voltage. A dc operating point must be set so that signal variations at the input terminal are amplified accurately reproduced at the output terminal. At dc operating point (Q-point), the collector current (IC) and collector-to-emitter voltage (VCE) have specified value.

DC Bias Bias establishes the dc operating point for proper linear operation of an amplifier. If an amplifier is not biased with correct dc voltages on the input and output, it can go into saturation or cutoff when an input signal is applied. Figure 5-1 shows the effects of proper and improper dc biasing of an inverting amplifier. In part (a), the output signal is an amplified replica of the input signal except that it is inverted, which means that it is 1800 out of phase with the input The output signal swings equally above and below the dc bias level of the output, VDC(out). Improper biasing can cause distortion in the output signal, as illustrated in parts (b) and (c). Part (b) illustrates limiting of the positive portion of the output voltage as a result of a dc operating point (Q-point) being too close to cutoff. Part (c) shows limiting of the negative portion of the output voltage as a result of a dc operating point being too close to saturation.

Fig 5-1a, b, & c Fig.5-1: Examples of linear and nonlinear operation of an inverting amplifier.

Fig.5-2: DC biased circuit. DC Bias Circuit Analysis To determine the output characteristics of a test circuit as illustrated in Fig. 5-2, we need to examine the relationship between the output current IC and the output voltage VCE, and the effect of the input voltage or current on this relation. The input voltages VBB and VCC are adjustable, so that we can control the input current IB and the output voltage VCE. Fig 5-2a & Fig 5-4 Fig.5-2: DC biased circuit.

Graphical Analysis The transistor in Figure 5-2(a) is biased with variable voltages VCC and VBB to obtain certain values of IB, IC, IE, and VCE. The collector characteristic curves for this particular transistor are shown in Figure 5-2(b); we will use these curves to graphically illustrate the effects of dc bias.

In Figure 5-3, we assign three values to IB, and observe what happens to IC and VCE. First, VBB is adjusted to produce an IB of 200 μA, as shown in Figure 5-3(a). Since IC= βDC IB, the collector current is 20 mA, as indicated, and VCE = VCC –ICRC = 10 V – (20 mA)(220 Ω) = 10 V – 4.4 V = 5.6 V This Q-point is shown on the graph of Figure 5-3(a) as Q1.

DC Load Line This dc load line is a straight line drawn on the characteristic curve from saturation value where IC = IC(sat) on y-axis to cutoff value VCE = VCC on x-axis. The dc operating point between saturation and cutoff is called the Q-point. The goal is to set the Q-point such that it does not go into saturation or cutoff when an a ac signal is applied. DC load line Fig 5-2a & Fig 5-4 Fig.5-3: DC load line.

Linear Operation The effect of a superimposed ac voltage, Vin, on VBB causes the IB to vary sinusoidally 100 µA above and below its Q-point value of 300 µA. This, in turn, causes the IC to vary 10 mA above and below its Q-point value of 30 mA. As a result of the variation in IC, VCE varies 2.2 V above and below its Q-point value of 3.4 V. Point A on the load line corresponds to the positive peak of the sinusoidal input voltage. Point B corresponds to the negative peak, and point Q corresponds to zero value of the sine wave. VCEQ, ICQ, and IBQ are dc-Q point values with no input sinusoidal voltage applied. Fig 5-5 circuit and load line w/signals 10 VCC Fig.5-4: Variation in IC and VCE as a result of a variation in IB.

Waveform Distortion In each cases, input signal is too large for Q-point location and is driving the transistor to cutoff or saturation during a portion of input cycle. Figure 5(c) –both peaks are limited. When only positive peak is limited , transistor is being driven into cutoff but not saturation. When only negative peak is limited, transistor being driven into saturation but not cutoff. Fig 5-5 circuit and load line w/signals Fig.5-5: Graphical load line illustration of a transistor being driven into saturation and/or cutoff.

5.2 Voltage-Divider Bias Fig.5-6: Voltage-divider bias. Voltage-divider bias is the most widely used type of bias circuit. Only one power supply is needed and voltage-divider bias is more stable than other bias types. A voltage divider can be formed by the combination of R1, R2 and VCC in the base circuit of the transistor, as shown in Fig. 5-6. A voltage divider bias circuits are designed so that IB is much smaller compared to I2 through R2 is said to be a stiff voltage divider because the base voltage is relatively independent of different transistor and temperature effects. Fig 5-9 Voltage-Div. Bias Fig.5-6: Voltage-divider bias.

Once the VB is known, VE can be found as Assuming that the loading effect of the transistor on the voltage divider is negligible, the voltage on base is calculated as: Once the VB is known, VE can be found as Using Ohm’s law, we can find IE as follows Fig 5-9 Voltage-Div. Bias VC = VCC - ICRC VCE = VC - VE

Voltage divider With Load Stiff: RIN(BASE) => 10R2 VB = R2 VCC R1 + R2 No Stiff: RIN(BASE) < 10R2 VB = R2 || RIN(BASE) VCC R1 + R2 || RIN(BASE)

5.3.1 Loading Effect of Voltage Divider Bias (a) DC Input Resistance at the Transistor Base When base to ground, the emitter resistor is viewed from the base circuit, the resistor appears to be larger than its actual value by a factor of βDC due to the current gain in the transistor. R IN(base) = (VIN/IIN) VIN= VBE+ IERE VIN ≈ IERE IE ≈ IC = βDC IB, VIN ≈ βDC IBRE The input current is the base current: IIN = IB RIN(BASE) = (VIN / IIN) = (βDC IBRE)/IB Fig 5-10a & b Fig.5-7: Voltage divider with load.

Fig.5.8: Thevenizing the bias circuit. (b) Stability of Voltage-Divider Bias Thevenin’s theorem is used to analyze a voltage divider biased transistor circuit for base current loading effects. Figure 5.8(b) shows the equivalent base emitter circuit for figure 5.8(a). (b) (c) (a) Fig 5-16 Fig.5.8: Thevenizing the bias circuit.

Apply Thevenin’s theorem to the circuit left of point A, the voltage at point A with respect to ground is and the resistance is Fig 5-16 Applying Khirchhoff’s voltage law around the equivalent base-emitter loop gives

Substituting IE/βDC for IB, Substituting, using Ohm’s law, and solving for VTH, Substituting IE/βDC for IB, Then solving for IE, Fig 5-16

(c) Voltage –Divider Biased PNP Transistor +VEE R2 RE + VBE VE VE = VB + VBE - VB IE = VEE –VE RE VC R1 RC VC = ICRC VEC = VE - VC

5.3 Other Bias Method Emitter Bias An emitter-bias circuit consists of several resistors and a dual-polarity power supply, as shown in Fig..Using KVL, we find For most transistors , so that IC = IE and defining IB in terms of IC and β produces Fig 5-21a npn emitter bias Solving for IC yields VE = VEE + IERE VB = VE + VBE VC = VCC - ICRC

Base Bias The simplest type of transistor biasing is base bias, or fixed bias. A base-bias circuit is shown in Fig. 5- . IC IB IE Current enters the circuit from VCC and splits, with the larger portion of the current passing through RC to the transistor collector and the rest passing through RB to the base. Then the currents exit the transistor emitter and return to ground. According to Ohm’s law, the value of IB can be found using Fig 5-19 Base bias circuit

Base Bias The voltage across RB equals the difference between VCC and VBE. By formula, IC IB IE Substituting Eq. into the Eq. gives us Once the value of IB is known, IC is calculated using Fig 5-2a & Fig 5-4 Finally, VCE can be found as

Emitter-Feedback Bias The emitter-feedback bias circuit is designed by adding an emitter resistor to the base-bias circuit. This circuit is used for the negative feedback. IB IE RE IC When IC increases, VE also increases, causing an increase in VB because VB = VE + VBE. This increase in VB reduces IB and keeping IC from increasing. To determine IE, KVL is used around the base circuit. Substituting IE/βDC for IB, we obtain

Collector-Feedback Bias The collector-feedback bias circuit is designed by connecting RB to the collector where this circuit obtain its Q-point stability. The analysis of this circuit begins with finding the value of IB. By Ohm’s law, IB can be expressed as Assuming IC >> IB. The collector voltage is Fig 5-23 collector feedback Also,

Substituting for VC and IB in Eq. and into Eq. , we obtain Then we can solve for IC as follows: Since the emitter is ground, VCE = VC.

Troubleshooting Fig. shows a voltage-divider bias circuit with correct voltage readings. It means that this circuit is operating properly. Fig 5-25

For the voltage-divider bias circuit, the faults that occur will cause VC equals VCC as shown in Fig below. Five faults are indicated for the circuit.

Summary The purpose of biasing is to establish a stable operating point (Q-point). The Q-point is the best point for operation of a transistor for a given collector current. The dc load line helps to establish the Q-point for a given collector current. The linear region of a transistor is the region of operation within saturation and cutoff. Voltage-divider bias is most widely used because it is stable and uses only one voltage supply. Base bias is very unstable because it is  dependent. Emitter bias is stable but require two voltage supplies. Collector-back is relatively stable when compared to base bias, but not as stable as voltage-divider bias.