Intel Siskiyou Peak CPU How to Run Simulation Chester Liu 2014/03/14

General Information Test environment Ubuntu 13.10 Download and uncompress source files In the following slides, ${SISKIYOU_TOP} means the directory where you place your uncompressed source files in

Tool Chain Prerequisite software packages Build tool chain libncurses5-dev bison & flex texinfo Use older texinfo (e.g. 4.13) if you encounter unknown command `colophon’ when building the tool chain llvm-3.1 & clang Build tool chain cd ${SISKIYOU_TOP}/toolchain/buildroot Use default configuration make menuconfig and exit (this will generate .config.cmd) cp configs/nano-newlib_defconfig .config; make Or customize your own configuration make menuconfig; make It takes a long time to complete

Environment Variables Set environment variables export HW_TOP=${SISKIYOU_TOP}/rtl export NANO_SHARED=${SISKIYOU_TOP}/toolchain/buildroot/output

RTL Prerequisite software package Compile RTL VCS-MX (e.g. 2013.06) mkdir ${SISKIYOU_TOP}/rtl/run cd ${SISKIYOU_TOP}/rtl/run ../sim/scripts/build.sh Remove -full64 from build.sh if running on 32-bit machine A file named simv should be created

RTL (contd.) Run RTL simulation for benchmark Dhrystone ./simv -ucli source ../sim/scripts/testbench.tcl load_elf_into_nc_memory ../sim/benchmarks/dhrystone/hw_obj/nano-O3/dhrystone.out Manual stop (press ctrl+c when you see “All assert checks passed”) run Or auto stop extract_labels_from_elf labels ../sim/benchmarks/dhrystone/hw_obj/nano-O3/dhrystone.out run_until_eip $labels(exit) exit

Dump Simulation Waveform Prerequisite software package Verdi (e.g. 2013.07) Modify ${SISKIYOU_TOP}/sim/tb/nc_base_top_tb.sv Add the following lines initial begin $fsdbDumpfiles(“waveform.fsdb”); $fsdbDumpvars; // dump RTL signals // $fsdbDumpvars(“+mda”); // plus dump multi-dimension arrays // $fsdbDumpvars(“+all”); // plus dump MDAs and structures end Modify ${SISKIYOU_TOP}/sim/scripts/build.sh Put the following lines in VCS_OPTIONS +vpi +vcsd +memcbk –P ${NOVAS_HOME}/share/PLI/VCS/LINUX/novas.tab ${NOVAS_HOME}/share/PLI/VCS/LINUX/pli.a Recompile and rerun RTL simulation

Compile Benchmark Use Dhrystone as example cd ${SISKIYOU_TOP}/rtl/sim/benchmarks/dhrystone Fix paths for nanoc and sysroot in do_all.sh with ${NANO_SHARED} ./do_all.sh

Run Assembly Code Simulation Modify ${SISKIYOU_TOP}/sim/tools/linker.ld Change comment style from // to /**/ to avoid syntax error Run RTL simulation cd ${SISKIYOU_TOP}/rtl/run ./simv -ucli source ../sim/scripts/testbench.tcl exec_assembly YOUR_ASSEMBLY_FILE exit

Sample Assembly Code # main.S .text xorl %eax, %eax # 31 C0 exit: nop # 90

Experiment Modify ${SISKIYOU_TOP}/rtl/src/core/pipeline_id.sv Change XOR (opcode = 8’h31) to behave like NOT Run the sample assembly code Normal XOR operation Should write 0 to EAX twice Modified XOR operation First write 0xffffffff to EAX, then write 0 to EAX

Simulation Result Normal XOR operation Modified XOR operation