طراحي و ساخت تراشه هاي VLSI (Design and Fabrication)

Slides:



Advertisements
Similar presentations
Chapter 6 Thermal oxidation and the Si/SiO2 interface
Advertisements

Homework: CMOS Fabrication Digital IC Design : Martin Page Discuss briefly the relationships between an ion beam’s acceleration potential, the beam.
ECE 6466 “IC Engineering” Dr. Wanda Wosik
CMOS Inverter Layout P-well mask (dark field) Active (clear field)
Simplified Example of a LOCOS Fabrication Process
CMOS Process at a Glance

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
EE213 VLSI DesignStephen Daniels 2003 VLSI Design Design Rules EE213 VLSI Design.
EE143 –Ali JaveySlide 10-1 Section 10: Layout. EE143 –Ali Javey Layout Design Rules (1) Absolute-Value Design Rules * Use absolute distances (2) -based.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley]
Project Title Name : University: Guide :. Introduction Project – what is new / what are you analyzing from this work – Example: Solar cell – increase.
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
Device Fabrication Example
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
Film Deposition in IC Fabrication
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Design Rules EE213 VLSI Design.
Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior.
FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR IC Fabrication n Basic fabrication steps. n Transistor structures. n VLSI Characteristics.
Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTR week2-1 Lecture 4 Transistor as Switch Jan
Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D. Deal, and P. B. Griffin Class: ECE 6466 “IC Engineering”
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.
RD50 funding request Fabrication and testing of new AC coupled 3D stripixel detectors G. Pellegrini - CNM Barcelona Z. Li – BNL C. Garcia – IFIC R. Bates.
Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.
CMOS VLSI Fabrication.
CMOS FABRICATION.
Patterning - Photolithography
CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from.
CMOS Fabrication EMT 251.
CMOS VLSI Design Lecture 2: Fabrication & Layout
Introduction to CMOS VLSI Design Lecture 0: Introduction.
EE314 IBM/Motorola Power PC620 IBM Power PC 601 Motorola MC68020 Field Effect Transistors.
The Devices: MOS Transistor
Basic Planar Processes
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
Process technology Physical layout with L-Edit
Manufacturing Process I
Prof. Haung, Jung-Tang NTUTL
20-NM CMOS DESIGN.
Layout and fabrication of CMOS circuits
Chapter 1 & Chapter 3.
VLSI Design MOSFET Scaling and CMOS Latch Up
MOSFET CAPACITANCES Very Large Scale Integration 1 - VLSI 1
Downsizing Semiconductor Device (MOSFET)
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
EE213 VLSI DesignStephen Daniels 2003 VLSI Design Design Rules EE213 VLSI Design.
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
LEC 3.2 LAYOUT D E S I G N R U L E S & DESIGN RULE CHECKER (DRC)
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Department of Electronic Engineering
CMOS半導體製程概念 INVERTER.
Manufacturing Process I
VLSI Lay-out Design.
V.Navaneethakrishnan Dept. of ECE, CCET
Network Flow-based Bipartitioning
Field Photos
Manufacturing Process I
CMOS Layers n-well process p-well process Twin-tub process.
Lecture 2 NMOS Technology VLSI, 2000
Presentation transcript:

طراحي و ساخت تراشه هاي VLSI (Design and Fabrication)

ساختار ترانزيستور nMOS

ساخت ترانزيستور هنگام رشد بلور، ناخالصي (نوع p) به آن داده مي شود. ناخالصي مثلاً بُر رشد يک لايه ي SiO2 بر سراسر ويفر. فوايد: عايق براي نشاندن لايه هاي ديگر و مانعي براي ناخالصي ها. زدودن قسمتي که ميخواهيم ترانزيستور در آن شکل گيرد. رشد يک لايه ي نازک SiO2

ساخت ترانزيستور روي لايه ي نازک SiO2 (Thinox) پلي سيليکون مي نشانيم (گيت ترانزيستور). بقيه اکسيد نازک را برمي داريم. در نتيجه نواحي مربوط به تشکيل نفوذ n رو باز مي مانند. پلي و تيناکس زير آن و اکسيد ضخيم (Fox) (Field Oxide) نقش نقاب را بازي مي کنند.

ساخت ترانزيستور عمل نفوذ (diffusion) : نواحي سورس و درين تشکيل مي شوند.

ساخت ترانزيستور رشد دوباره ي Fox براي عايق بندي.

ساخت ترانزيستور باز گذاشتن محلهايي براي قرار دادن اتصالات.

ساخت ترانزيستور نشاندن فلز (Al) روي سطح ويفر با الگوي مطلوب.

الگوبندي

الگوبندي

الگوبندي

الگوبندي

الگوبندي

فلز سطح دوم براي فلز سطح دوم، روي ويفر با Fox پوشانده مي شود. جاهايي که فلز سطح 2 بايد به فلز سطح 1 متصل باشد حفره هايي به نام Via Cut ايجاد مي شوند. فلز سطح 2 ايجاد و الگوبندي مي شود.

اتصالات چندلايه

اتصالات چندلايه ي مسي

ساخت ترانزيستور http://micro.magnet.fsu.edu/electromag/java/transistor/index.html