CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

The MOS Transistors

The MOS Transistors

CMOS Device Model Objective CMOS transistor models Hand calculations for analog design Non-idealities and their effects Efficient and accurate simulation CMOS transistor models Large signal model Small signal model Simulation model Noise model

Large Signal Model Nonlinear equations for solving dc values of device currents, given voltages Level 1: Shichman-Hodges (VT, K', g, l, f, and NSUB) Level 2: with second-order effects (varying channel charge, short-channel, weak inversion, varying surface mobility, etc.) Level 3: Semi-empirical short-channel model Level 4: BSIM models. Based on automatically generated parameters from a process characterization. Good weak-strong inversion transition.

Gate contact is always placed off gate area! Device is symmetric. Higher voltage side is drain, lower voltage side is source. BSIM5 and PSP models will enforce this symmetry.

Transconductance when VDS is small This shows when VGS=0. As VGS, depletion region appears under gate oxide. When VGS=VT, an inversion layer begins to appear under gate oxide. This is sub-threshold.

Sub-threshold PN junction depletion region completely surrounds drain area and source area Current from D to S is nearly 0 Tiny diode currents come out of drain and out of source PN junction at D is more negatively biased, so less diode current out of D So net positive current from D to S

Sub-threshold Diode current is an exponential function of PN junction voltage When VGS not =0, PN junction voltage not uniform Highest PN junction voltage happens near the corner by the gate

Transconductance when VDS is small

Voltage controlled resistor and attenuator

Non-uniform channel potential non-uniform gate-substrate voltage and non-uniform threshold voltage

Good for VDS <VGS-VTH After that, ID become saturated.

Linear in deep triode Pro: voltage control of resistivity. Con: nonlinear resistor.

MOST Regions of Operation Cut-off, or non-conducting: vGS <VT iD=0 approximately Conducting, or on: vGS >=VT Saturation: vDS > vGS – VT Triode or linear or ohmic or non-saturation: vDS <= vGS – VT

With channel length modulation

iD vs vGS for several VDS Square function But when vGS-VT > VDS: Straight line

iD vs vDS for several VGS gds gm*DVGS

iD vs vDS for several VGS -VA

Influence of Channel Length on l Lmin = 0.25 Johns and Martin book gives an approximate formula with l  1/L At >=2*Lmin, l is small, Ro is large After 1um, l remains about the same

Influence of VBS VBS changes threshold voltage, and hence changes i-v curve.

Temperature Dependence of Mobility Linear Temperature Dependence of threshold voltage Saturation Velocity Junction capacitance Barrier potential Drain resistance

This is nonlinear if Vbs is temperature dependent

Typical VT and ß temperature performance

Referenced from Filanovsky’s paper 0.35um process ZTC biasing Referenced from Filanovsky’s paper

Reality: no single point crossing Not just one single crossing ID In AMI0.6 process Test on a single NMOS biased with fixed Vgs and Vds Vgs

To refine the value AMI 0.6 Vgs=1.12V Vgs=1.14V Optimum curve TC = 41 ppm/C Vgs=1.17V

Generic 018 Vgs=0.717V Vgs=0.721V TC=27 ppm/C Vgs=0.727V

Large signal model for approximate hand caculation

Capacitors Of The MOSFET

C2 is the capacitance between the gate and the channel. C2 is not directly measurable. C4 is the capacitance between the channel and the bulk. It is highly nonlinear and depends on the operation of the device. C4 is not measurable from terminals. C2 and C4 in series give part of CGB that can be measurable.

CBD and CBS include both the diffusion-bulk junction capacitance as well as the side wall junction capacitance. They are highly nonlinear in bias voltages.

Gate related capacitances

Capacitors in Cutoff

Capacitors in Saturation

Capacitors in Triode

Small signal model

Typically: VDB, VSB are in such a way that there is a reversely biased pn junction. Therefore: gbd ≈ gbs ≈ 0

In saturation: But

Intrinsic DC voltage gain: gm/gds = gm*rds

In non-saturation region

Transistor performance Intrinsic gain Speed / bandwidth gm efficiency Linearity Area, Power Matching

Intrinsic gain For large gain, use small ID or small over drive voltage, or in moderate to weak inversion.

High Frequency Figure of Merit wT AC current source input to G AC short S, D, B to gnd (i.e. constant voltages) Measure AC drain current output Calculate current gain Find frequency at which current gain = 1. Ignore rs and rd,  Cbs, Cbd, gds, gbs, gbd all have zero voltage drop and hence zero current Vgs = Iin /jw(Cgs+Cgb+Cgd) ≈ Iin /jw(Cgs+Cgd) Io = − (gm − jwCgd)Vgs ≈ − gm Iin /jw(Cgs+Cgd) |Io/Iin| = |gm − jwCgd|/w(Cgs+Cgd) ≈ gm/w(Cgs+Cgd)

amplification |Io/Iin| attenuation wT 0 dB w

At wT, current gain =1 wT ≈ gm/(Cgs+Cgd)≈ gm/Cgs or

For fastest operation, use Vod near but before fT peak For power efficiency, use Vod before fT corner

High Frequency Figures of Merit wmax AC current source input to G AC short S, B to gnd Measure AC power into the gate Assume complex conjugate load Compute max power delivered by the transistor Find maximum power gain Find frequency at which power gain = 1.

gdo vs gm in short channel

gdo vs gm in short channel

Insights: gdo increases all the way with current density Iden gm saturates when Iden larger than 100mA/mm Velocity saturation, mobility degradation ---- short channel effects Low gm/current efficiency High linearity For power efficiency and gm efficiency Use moderate to low current density Use small over drive voltage

To Av: (W/L), m, ID, l, set VoQ at mid rail For high speed: Veff, m; L, Cgd, rg For better linearity: Vds, Vdb, set VoQ at mid rail Veff range: <~0.5V; or <~0.3V for efficiency ID/W range: <100mA/mm; or <40mA/mm for efficiency

BSIM models Non-uniform charge density Band bending due to non-uniform gate voltage Non-uniform threshold voltage Non-uniform channel doping, x, y, z Short channel effects Charge sharing Drain-induced barrier lowering (DIBL) Narrow channel effects Temperature dependence Mobility change due to temp, field (x, y) Source, drain, gate, bulk resistances

“Short Channel” Effects VTH decreases for small L Large offset for diff pairs with small L Mobility reduction: Velocity saturation Vertical field (small tox=6.5nm) Reduced gm: increases slower than root-ID

Threshold Voltage VTH Strong function of L Process variations Use long channel for VTH matching But this increases cap and decreases speed Process variations Run-to-run How to characterize? Slow/nominal/fast Both worst-case & optimistic

Effect of Velocity Saturation Velocity ≈ mobility * field Field reaches maximum Emax (Vgs-Vt)/L reaches ESAT gm become saturated: gm ≈ ½mnCoxW*ESAT But Cgs still 2/3 WL Cox wT ≈ gm/Cgs = ¾ mnESAT /L No longer ~ 1/L^2

Threshold Reduction When channel is short, effect of Vd extends to S Cause barrier to drop, i.e. Vth to drop Greatly affects sub-threshold current: 26 mV Vth drop  current * e 100~200 mV Vth drop due to Vd not uncommon  100’s or 1000 times current increase Use lower density active near gate but higher density for contacts

Other effects Temperature variation Normal-Field Mobility Degradation Substrate current Very nonlinear in Vd Drain to source leakage current at Vgs=0 Big concern for static power Gate leakage currents Hot electron Tunneling Very nonlineary Transit Time Effects

Consequences for Design SPICE (HSPICE or Spectre) BSIM3, BSIM4 models Accurate but inappropriate for hand analysis Verification (& optimization) Design: Small signal parameter design space: gm, CL (speed, noise) gm/ID, ID (power, output range, speed) Av0= gmro (gain) Device geometries from SPICE (table, graph); may require iteration (e.g. CGS)

Intrinsic voltage gain of MOSFET Sweep V1 Measure vgs Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id

Intrinsic voltage gain of MOSFET Sweep V1 Measure vgs + - Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id

Weak inversion When VGS is reduced to Vth, the drain current does not go to zero It does not follow square law It does not follow exponential law When VGS is markedly below Vth, the drain current becomes an exponential function of VGS. Behaves very much like a diode

A model from weak to strong inv

In strong inversion In strong inversion, n is about 1

In weak inversion

In weak inversion If vt = 25mV, n=2, gm/ID = 20 n=1.5, gm/ID = 27

ID vs VGS Exponential model Square law model simulation

ID/(W/L) vs VG is sensitive to VBS

gm/ID vs VG is also sensitive to VBS

But gm/ID vs ID/(W/L) has fixed shape

Related VDD insensitive circuits Filanovsky, etc, “Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits”. G. Giustolisi “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs”. Ka Nang Leung “A CMOS Voltage Reference Based on Weighted VGS for CMOS Low-Dropout Linear Regulators”. Bernhard Boser. “Analog Circuit Design with Submicron Transistors". IEEE SSCS Meeting, Santa Clara Valley, May 2005.

TSMC 0.18 um Process

TSMC 0.18 um Process

TSMC 0.18 um Process

TSMC 0.18 um Process

TSMC 0.18 um Process

TSMC 0.18 um Process