Washington University CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington University Fall 2002 http://www.arl.wustl.edu/~lockwood/class/cs536/ Chris Neely, Chris Zuver Copyright 2002 Lockwood@arl.wustl.edu

MP1 Packet classification hardware 103 CAM_MASK_1 103 CAM_VALUE_1 Drop 103 72 71 40 39 8 7 Src IP Dest IP Src Port Dest Port Proto 103 CAM_VALUE_2 103 CAM_MASK_2 match <= ‘1’ when (input = 0xFFFFFFFFFFFFFFFFFFFFFFFFFF”) else ‘0’;

Protocol Headers Cell Header IP Header UDP IP Header Payload PAD AAL5 Trailer AAL5 Pad CPS-UU & CPI Frame Len AAL5 AAL5 Frame Checkum

State Transitions for processing Packet

Additional Notes on the Protocol Wrappers NOTE: Check SOD DataEn SOF EOF Data SOC SOD SOP/ A I U D - P F ATM Header IP Header Don't care Frame Trailer Padding Payload Data UDP Header CLK Cell Level Frame Level IP Level Data Enabled during frame trailer Only use these signals to process UDP/IP packets This cycle is optional. It does not appear in simulation UDP payload starts 2 cycles after SOP signal. UDP payload ends with EOF signal.

CAM Update Datagram ATM Header Packet Len Source IP address 192.168.30.13 ( 0xC0A81E0D ) (Reserved) CAM_1_SRC_IP CAM_MASK_1 … (if necessary) ToS HL Ver Fragment IP ID Src Port Dest Port ( 0x0320 ) Length Checksum # CAMs AAL5 Pad CPS-UU & CPI AAL5 Frame Checksum Frame Len CAM_1_DEST_IP CAM_1_PORTS CAM_1_ PROTO (PAD) CAM_2_SRC_IP CAM_MASK_2 CAM_2_DEST_IP CAM_2_PORTS CAM_2_ PROTO } CAM_VALUE_1 CAM_VALUE_2 Special UDP/IP Datagram updates values of CAM Entries Allows software-controlled update of CAM registers Fields alocated for: CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2

State Transitions for updating CAMs

FPX Hardware Design Flow Compile circuit (vcom) Verify Functionality (vsim) Constrain Placement to FPX RAD Verify that that resulting packets have correct TTL Test Module with actual traffic input Synthesize Logic to Xilinx gate technology (Synplicity) Upload bitfile To FPX for testing Place and Route with constraints (Xilinx) Verify Post Place & Route Timing (ModelSim) Generate bitstream (Xilinx)

Downloading and extracting MP1 files

Accessing FPGA Design Tools in Sever 201 Tools -> Class -> … Opening Cygwin and

Compiling the design Compiling the tools Simulating the Design make compile Simulating the Design make sim

ModelSim Simulation Screenshots from ModelSim

The Testbench Sample format of Data Input

Synthesizing the Design Screen shots from Synplicity

Backend Tools : Generating the Bitstream

Testing the design on the FPX Screen shots of the upload

Verifying the Results Screenshots ..

Creating the waveforms Creating waveforms…

Uploading your solutions Open the page http://www.gradebot.com/cs536/submit/upload.cgi