8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board DMB Production 8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board 550 Production Boards S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

DMB Production Boards 411/550 boards delivered/tested 70 boards required repair Board are being boxed and stored until needed at Ohio State Production Schedule S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

It’s Alive ! New Crate Controller Development A VMEbus Controller with Gigabit Ethernet A custom board designed and developed at OSU Based on XILINX Virtex-II Pro Custom firmware. Optical transceiver (for Gbit Ethernet) Communicates with stand-alone PC (in USC55) via Gigabit Ethernet It’s Alive ! Measured: Continuous Read/Write VME Transfers at 120 Mbit/s S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

Gigabit-VME Ethernet Protocol Utilize Commercial Software (Drivers) Ethernet Raw Socket Layer (requires setuid();) Packet to Controller: Ethernet Header Header2 VME Write 1 VME Read 2 VME Delay 3 VME Write 4 Dest Addr | SRC Addr | PktLen RSVD | NVME Cntrl | VME Addr | Data Cntrl | VME Addr Cntrl | VME Delay Cntrl | VME Addr | Data  14 bytes 4 bytes 8 bytes 6 bytes 4 bytes 8 bytes Packet from Controller: Ethernet Header Header2 Data from VME … Dest Addr | SRC Addr | PktLen RSVD | NWrds Data Data Data Data Data Data Data Data Data Data  14 bytes 6 bytes 2 bytes 2 bytes … 8 bytes 8 bytes Note: Jumbo Packet Support 9000 bytes S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

Controller Production Schedule New Controller has Run in DDU/DCC Crate for 1 Month - Very Stable, No Bus Hangs or Resets Needed Yet! - Radiation Tests Need to be Performed Firmware Additions Needed: - Storage of MAC Address in SRAM - Controller Handshake for Overflow Protection Production Schedule S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

DDU Prototype Functions Merge data from 13 DMBs SLINK Mezz Board Optical Fiber Input (15) GbE To Local DAQ Input FIFOs FPGA FIFO Main FPGA VME FMM output port Functions Merge data from 13 DMBs Perform error checking and status monitoring (CRC, word count, L1 number, BXN, overflow, link status) Communicates w/FMM Large Buffer Capacity 2.5 MB buffer Average DDU data volume estimated to be 0.4kB per L1A at LHC (@1034 lumi) Buffer can hold over 6000 events TTC signals from DCC Slow control via VME S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

DCC Prototype Data Concentration Fast Control Merge data from 9 DDUs J1 backplane SLINK TTCrx Control FPGA Output FIFOs Input FPGAs VME DDU data Data Concentration Merge data from 9 DDUs send merged data to central DAQ via 1 or 2 SLINKs Has two optional GbE spy data path Fast Control Receive TTC fiber signals using TTCrx, Fanout L1A, LHC_clock and other TTC signals to DDUs Has optional FMM interface S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

DDU/DCC Prototype - very successful, no problem for > 10x LHC rate DDU/DCC TestBeam 2004 - very successful, no problem for > 10x LHC rate Both DDU/DCC Passed ESR Nov. 2004 DDR FIFO bit errors – bad chip used on DDU/DCC/Controller (72T40/20 family) IDT72T40118, 40-bit 0.5MByte, DDR FIFO bit errors, esp. bit 21 Detailed test on test board Error shown on DDU and VME_controller (DDR FIFO) Still working with IDT Replacement: TI SN74V3690 IDT 72V36110 FIFO Qout[39:20] LFSR parity COMP D[39:20] Q[39:20] Din[19:0] Qout[19:0] D[19:0] Q[19:0] FIFO Write/read Error report S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005

( * : pre-production boards) DDU/DCC Production Relayout Both DDU and DCC optional baseline C O N T R L E D U Detector Dependent Unit (DDU) 9/crate, 50 will be built Data Concentration Card (DCC) 1 or 2/crate, 10 will be built Production Schedule ( * : pre-production boards) S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005