Teaching The Art of Verification

Slides:



Advertisements
Similar presentations
TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.
Advertisements

1 System Level Verification of OCP-IP based SoCs using OCP-IP eVC Himanshu Rawal eInfochips, Inc.,4655 Old Ironsides Drive, Suite 385,Santa Clara, CA
April 30, A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab.
2009 – E. Félix Security DSL Toward model-based security engineering: developing a security analysis DSML Véronique Normand, Edith Félix, Thales Research.
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
1 of 24 The new way for FPGA & ASIC development © GE-Research.
1 Speed, Drunkenness, and the Wall Does High Level Design/ESL Make Sense? Kris Konigsfeld Sr. Principal Engineer Oregon CPU Architecture Intel Corporation.
Liang, Introduction to Java Programming, Sixth Edition, (c) 2007 Pearson Education, Inc. All rights reserved Chapter 1 Object-Oriented.
Title of Presentation Presenter Matthew J Morley Teaching Functional Verification Workshop DAC 2002, Sunday June 9 th. Testbench Automation Concepts.
Software Testing and Quality Assurance
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
Calc2 Design Allows up to 4 incomplete requests on each port Tag is required to match request to response.
EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,
Matlab as a Design Environment for Wireless ASIC Design June 16, 2005 Erik Lindskog Beceem Communications, Inc.
Principle of Functional Verification Chapter 1~3 Presenter : Fu-Ching Yang.
VerificationTechniques for Macro Blocks (IP) Overview Inspection as Verification Adversarial Testing Testbench Design Timing Verification.
Database Actors Database Administrators Database Designers
1 FIPS 140 Validation for a “System-on-a-Chip” September 27, 2005 NIST Physical Testing Workshop.
VHDL Structured Logic Design School of Electrical Engineering University of Belgrade Department of Computer Engineering Ivan Dugic Veljko.
Revolutionizing the Field of Grey-box Attack Surface Testing with Evolutionary Fuzzing Department of Computer Science & Engineering College of Engineering.
1CADENCE DESIGN SYSTEMS, INC. Cadence Proposed Transaction Level Interface Enhancements for SCE-MI SEPTEMBER 11, 2003.
Some Course Info Jean-Michel Chabloz. Main idea This is a course on writing efficient testbenches Very lab-centric course: –You are supposed to learn.
Design Verification An Overview. Powerful HDL Verification Solutions for the Industry’s Highest Density Devices  What is driving the FPGA Verification.
Copyright © 2002 Qualis Design Corporation Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone:
SoC Verification HW #2 TA: Wei-Ting Tu Assignment: 04/12/06
Teaching Functional Verification Design Automation Conference Sunday, June 9, 2002.
FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR Topics n Design methodologies.
1 Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210)
Reporter: PCLee. Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use.
Guiding Principles. Goals First we must agree on the goals. Several (non-exclusive) choices – Want every CS major to be educated in performance including.
Functional Verification Figure 1.1 p 6 Detection of errors in the design Before fab for design errors, after fab for physical errors.
Quality Driven SystemC Design By Nasir Mahmood. Hybrid Approach The idea here is to combine the strengths of simulation – namely the ability to handle.
©2002 B&R Software Technology - Automation Studio.
Verification Environment Architecture Sergey Nemanov December 21, 2005 Verification Leadership Seminar.
ICS 216 Embedded Systems Validation and Test Instructor: Professor Ian G. Harris Department of Computer Science University of California Irvine.
An Overview of Hardware Design Methodology Ian Mitchelle De Vera.
1 Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210)
Design - programming Cmpe 450 Fall Dynamic Analysis Software quality Design carefully from the start Simple and clean Fewer errors Finding errors.
Macro Verification Guidelines Chapter 7.. Chap 7. Macro Verification Guidelines The goal of macro verification The macro is 100 percent correct in its.
UNIT-1 SOFTWARE PRODUCT AND PROCESS: Introduction – S/W Engineering paradigm – Verification – Validation – Life cycle models – System engineering –
Chapter 11 System-Level Verification Issues. The Importance of Verification Verifying at the system level is the last opportunity to find errors before.
1 Memory Test - Debugging Test Vectors Without ATE Steve Westfall Director Visual Testbench Engineering Summit Design Inc.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
1 of 24 The new way for FPGA & ASIC development © GE-Research.
Practical Methods in Coverage- Oriented Verification of the Merom Microprocessor Alon Gluska.
SDN challenges Deployment challenges
Instructor Materials Chapter 8: Network Troubleshooting
The architecture of the P416 compiler
Digital System Verification
Lect 11 - Stimulus & Response
environment infrastructure
Top-Down Network Design Chapter Nine Developing Network Management Strategies Copyright 2010 Cisco Press & Priscilla Oppenheimer.
Formal Methods (i.e. mathematical, algorithmic) for Software and Hardware Designs and, more generally, Design Tools and Technologies
Introduction CSE 1310 – Introduction to Computers and Programming
February 25-28, 2013 DoubleTree, San Jose
Figure 1 PC Emulation System Display Memory [Embedded SOC Software]
Peter J. Ashenden The University of Adelaide
Matlab as a Design Environment for Wireless ASIC Design
Verification Reuse Simple (relatively) reuse: Difficult reuse
An Embedded Systems Course and Course
CS 501: Software Engineering Fall 1999
SystemVerilog for Verification
Verification Plan & Levels of Verification
Lect 11 - Stimulus & Response
Teaching Functional Verification – Course Organization
Srinivas Aluri Jaimin Mehta
L9 - Verification Strategies
Computer Systems Performance Evaluation
SystemVerilog and Verification
Top-Down Network Design Chapter Nine Developing Network Management Strategies Copyright 2010 Cisco Press & Priscilla Oppenheimer.
Presentation transcript:

Teaching The Art of Verification Faisal Haque Workshop on Teaching Verification DAC 2002

The Verification Space Test plans Test cases HVL (VERA) Testbenches Simulators RTL Coverage Functional Coverage Bug tracking Revision Control Regressions Debuggers Waveform viewers Build tools Directory Structure Covered in detail in The Art of Verification with Vera Covered at an introductory level 11/12/2018©2002 Verification Central All rights reserved

Why We Wrote The Book Large ASIC verification requires a different approach than used in past Teach verification methodology for large ASICs Teach testbench implementation using real life designs 11/12/2018©2002 Verification Central All rights reserved

Premise Verification is an art and a science Creativity (art) in optimizing testbenches Determinism (science) for repeatability Tremendous complexity growth requires changes in our approach to verification 11/12/2018©2002 Verification Central All rights reserved

Our Verification Model Planning Verification Plan # of Testbenches Test Cases Testbenches Create test cases Run and debug test cases Testing Functional Coverage Regression Coverage and Regression 11/12/2018©2002 Verification Central All rights reserved

Our Testbench Model Modularization High degree of concurrency Under Test Design Generator packets transactor 0101010 0101010 transactor packets Monitor Automatically generates stimulus Operates at a higher level of abstraction Converts stimulus to binary vectors Interfaces to DUT Converts binary response to transactions Interfaces to DUT Checks Response Typically implements some reference model of DUT Operates at a higher level of abstraction Point generators and Transactor and monitors all run as independent processes Typically generator and monitors operate at a higher level of abstraction. Transactor deal with the DUT and its transaction protocols. Separate transactors mean you can use all different stimuli and feed into xactor Modularization High degree of concurrency Architecture driven by checking policy 11/12/2018©2002 Verification Central All rights reserved

What Students Need to Learn About Functional Verification (Beyond Software Engineering) Identify testbenches and test cases Manage the trade offs between number of testbenches and complexity Create an architecture for the testbench(es) Understand stimulus generation techniques Understand result checking techniques How to analyze coverage 11/12/2018©2002 Verification Central All rights reserved

What the Book Covers Simulation based verification Verification methodology Test plan Test cases Stimulus generation Coverage analysis Implementation Vera language Implementation of real testbenches with Vera 11/12/2018©2002 Verification Central All rights reserved

Suggested Reading Paths Chapters 1,2, 3 Testbenches Test cases Stimulus, monitors Chapter 8 Chapter 12 Random Stimulus Generation Chapter 13 Result Checking Chapter 14 Coverage & Regressions Debugging Time 11/12/2018©2002 Verification Central All rights reserved

Examples and Labs Most simple concepts are explained using small examples Main example is an Ethernet MAC Test plan to implementation Other examples are CPU and Ethernet switch Most of the examples can be used as labs 11/12/2018©2002 Verification Central All rights reserved

About the Authors Faisal Haque Khizar khan Jon Michelson Over 18 years of experience. Currently involved in design and verification of complex systems at Cisco system Khizar khan Over 7 years of experience. Currently involved in verification of complex microprocessors at sun Jon Michelson Over 7 years of experience. Currently involved in verification and design of complex systems at Cisco system 11/12/2018©2002 Verification Central All rights reserved