Teaching The Art of Verification Faisal Haque Workshop on Teaching Verification DAC 2002

The Verification Space Test plans Test cases HVL (VERA) Testbenches Simulators RTL Coverage Functional Coverage Bug tracking Revision Control Regressions Debuggers Waveform viewers Build tools Directory Structure Covered in detail in The Art of Verification with Vera Covered at an introductory level 11/12/2018©2002 Verification Central All rights reserved

Why We Wrote The Book Large ASIC verification requires a different approach than used in past Teach verification methodology for large ASICs Teach testbench implementation using real life designs 11/12/2018©2002 Verification Central All rights reserved

Premise Verification is an art and a science Creativity (art) in optimizing testbenches Determinism (science) for repeatability Tremendous complexity growth requires changes in our approach to verification 11/12/2018©2002 Verification Central All rights reserved

Our Verification Model Planning Verification Plan # of Testbenches Test Cases Testbenches Create test cases Run and debug test cases Testing Functional Coverage Regression Coverage and Regression 11/12/2018©2002 Verification Central All rights reserved

Our Testbench Model Modularization High degree of concurrency Under Test Design Generator packets transactor 0101010 0101010 transactor packets Monitor Automatically generates stimulus Operates at a higher level of abstraction Converts stimulus to binary vectors Interfaces to DUT Converts binary response to transactions Interfaces to DUT Checks Response Typically implements some reference model of DUT Operates at a higher level of abstraction Point generators and Transactor and monitors all run as independent processes Typically generator and monitors operate at a higher level of abstraction. Transactor deal with the DUT and its transaction protocols. Separate transactors mean you can use all different stimuli and feed into xactor Modularization High degree of concurrency Architecture driven by checking policy 11/12/2018©2002 Verification Central All rights reserved

What Students Need to Learn About Functional Verification (Beyond Software Engineering) Identify testbenches and test cases Manage the trade offs between number of testbenches and complexity Create an architecture for the testbench(es) Understand stimulus generation techniques Understand result checking techniques How to analyze coverage 11/12/2018©2002 Verification Central All rights reserved

What the Book Covers Simulation based verification Verification methodology Test plan Test cases Stimulus generation Coverage analysis Implementation Vera language Implementation of real testbenches with Vera 11/12/2018©2002 Verification Central All rights reserved

Suggested Reading Paths Chapters 1,2, 3 Testbenches Test cases Stimulus, monitors Chapter 8 Chapter 12 Random Stimulus Generation Chapter 13 Result Checking Chapter 14 Coverage & Regressions Debugging Time 11/12/2018©2002 Verification Central All rights reserved

Examples and Labs Most simple concepts are explained using small examples Main example is an Ethernet MAC Test plan to implementation Other examples are CPU and Ethernet switch Most of the examples can be used as labs 11/12/2018©2002 Verification Central All rights reserved

About the Authors Faisal Haque Khizar khan Jon Michelson Over 18 years of experience. Currently involved in design and verification of complex systems at Cisco system Khizar khan Over 7 years of experience. Currently involved in verification of complex microprocessors at sun Jon Michelson Over 7 years of experience. Currently involved in verification and design of complex systems at Cisco system 11/12/2018©2002 Verification Central All rights reserved