EEL 3705 / 3705L Digital Logic Design Spring 2007 Instructor: Dr. Michael Frank Modules #90-99 (Extra Slides): Design Examples Module #94: PS/2 Serial Port Receiver and Keyboard Byte Sequence Decoder 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Keyboard and Mouse Input Using the PS/2 Port PS/2 Serial Line Receiver Circuit and Keyboard Byte Sequence Decoder 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 PS/2 Port Pins From UP2 User’s Guide, p.13… 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

PS/2 Serial Port – Physical/Electrical Specifications For text of specs, see http://www.computer-engineering.org/ps2protocol/ 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Verifying the On-Board Port Circuitry We check the UP2 board schematics and see that there is no port-driving circuitry between the PS/2 port and the FLEX chip The pullup resistors for the open-drain output drivers must be implemented internally within the FLEX chip UP2 board schematics, page 6 UP2 board schematics, page 1 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

PS2 Electrical Interface in Quartus Entity ps2_port: in example project VGA_char_RAM2 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

PS/2 Serial Line Protocol Host controls bus: Data 1, Clock 1 Device may transmit data Data 1, Clock 0 Device may not transmit data Data 0, Clock 1 Host requests device to send clock pulses so host may transmit data Device generates clock pulses: 10-16.7 kHz, 50% duty cycle 1 data bit sent per clock cycle Data bit is most likely to be valid in the middle of the clock’s low period Invalid during high period Data packet framing: 1 start bit (always 0) 8 data bits, LSB first 1 parity bit (odd parity) 1 stop bit (always 1) 1 1 1 1 00010101 = 1516 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Signal Decoding Strategy Wait 20 µs after falling clock edge before sampling data bit value Gives the best chance of being in the valid region for either slow or fast clocks • Wait until rising clock edge after bit #11 before declaring frame is complete. Slow clock (10 kHz): 100 µs 100 µs … 50 µs 50 µs bit #0 (between frames) bit #1 bit #2 bit #11 bit #0 25 µs Fast clock (16.7 kHz): • Wait 100 µs after rising clock edge before resetting bit counter 60 µs … 30 µs 30 µs bit 1 bit 2 bit 11 15 µs 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

PS/2 Serial Line Receiver Circuit (Byte Deframer/Deserializer) Entity ps2_reader in VGA_char_RAM2_v6: 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

PS/2 Keyboard Make/Break Codes Here are some representative examples: From http://www.computer-engineering.org/ps2keyboard/scancodes2.html Key Make (Key Press) Code Break (Key Release) Code A a 1C F0,1C Right Ctrl E0,14 E0,F0,14 Print Screen / SysReq E0,12,E0,7C E0,F0,7C,E0,F0,12 Pause / Break E1,14,77,E1,F0,14,F0,77 None (not detectable) Additional undocumented variants of the normal code sequences may also be produced for certain keys, depending on whether the Num Lock key is active. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Map Between Single-Byte Make Codes and Key Cap Labels You can use this table to quickly look up what make code is generated by a given key. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Displaying Received Bytes as ASCII Characters Additions to top-level circuit in VGA_char_RAM2_v3 This counter keeps track of what RAM byte address (0-127) the next byte received will be written to… 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Output from VGA_char_RAM2_v3 Press/release “D key” Double F016 bytes: Possible timing problem? User typed, “donte␣rules1” Key M/B Hex ASCII char D d Make 23 # Break F0 p O o 44 D N n 31 1 T t 2C , E e 24 $ 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Keyboard Byte Sequence Decoder Finite State Machine Diagram 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Single-Byte ASCII-based Representation of the Map 1 key make codes This determines what character is displayed on screen by the VGA_char_ram2_v6 project when a given key is pressed. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Map from 2nd byte of 2-byte make codes to chosen ASCII representations 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Circuit for Keyboard Make/Break Byte Sequence Decoder State Machine Entity key_decoder in VGA_char_RAM2_v6 This is a good example of a design that badly needs to be modularized for better readability! View circuit in Quartus to zoom in on particular parts 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Synchronous Delay Circuit Entity delayed_pulse in VGA_char_RAM2_v6 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Relevant part of Top-Level Circuit Byte stream is filtered through key_decoder 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Output from VGA_char_RAM2_v6 User typed, “donte␣rules1” Output consists of the ASCII characters assigned to represent each key Inverse video denotes key release events 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Simplified State Machine Design for key_decoder_v2 Only three state bits are really needed: f0 – Last byte was F016; we will output a break code. e0 – We’re in an extended byte-code sequence, starting E016 or E116. Use Map 2 instead of Map 1 for translating final byte of sequence. e1 – Last byte seen (except maybe F0) was E116 Ignore next small byte seen (14 in Pause/Break sequence) 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Descriptions of All the Possible States In the below, state bits are given in the order e1e0f0: 000 – Default state, in between byte sequences. 001 – After 1st byte (F0) of a map 1 break code. 010 – After E0 in an extended (map 2) sequence. Or after E1,14 in the Pause/Break sequence. 011 – After E0,F0 in an extended (map 2) sequence. Or after E1,F0,14 in the Pause/Break sequence/ 10d – (these states are not currently used) 110 – After E1 in an extended (map 2) sequence. 111 – After E1,F0 in an extended (map 2) sequence 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

State Diagram for Simplified Machine Here is the complete state-transition diagram for the expected code sequences Actually, due to the don’t-cares, many other codes would also cause the specific transitions shown… But these shouldn’t occur in practice. <80 map1 break <80 map1 make State 001 (1) State 000 (0) F0 E1 State 110 (6) E0 <80 map2 break <80 map2 make State 010 (2) 14 F0 State 011 (3) F0 State 111 (7) 14 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Example State Sequence User presses & releases keys: State bits are shown in the yellow columns as: e1e0f0 Input bytes are in blue, output characters are B&W 000 1C F0 001 A E0 010 14 011 ] 12 7C  ⌥ E1 110 77 111 ⊜ A a Break sequences outlined in red Right Control Print Screen SysRq Pause Break “fake break” sequence from Pause/Break 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Next-State Logic Useful temporary variables: low_byte = ~b7 (byte less than 80x); hi_byte = b7 & b6 (byte C0x or higher) Product terms for rows of truth table: norm_byte = ~e1 & low_byte (1st row) 83_byte = b7 & ~b6 (2nd row) skip_byte = e1 & low_byte (3rd row) F0_byte = hi_byte & b4 (4th row) E_byte = hi_byte & ~b4 (5th row) Logic for determining the next-state bits based on the above: e0* = e1 | (~norm_byte & (e0 | E_byte)) Either we were just in e1 mode, or the byte just received was not a normal byte, and either we were already in E0 mode, or we just received an E0 or E1 byte. e1* = hi_byte & (e1 | (E_byte & b0)) The byte just seen was a high one, and either we were already in E1 mode, or we just received an E1 byte. f0* = F0_byte The byte just seen was an F0. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Core of key_decoder_v2 FSM 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Output of VGA_char_RAM3_v5 A large, complete 7-bit ASCII table is displayed Including my custom control characters & associated colors. Circuit keeps track of which keys are currently depressed And highlights the ASCII character assigned to each in my encoding Using inverse video In this snapshot, user is holding down the keys “A,” “C,” “E.” User must also have pressed the FLEX_PB1 pushbutton to clear the display initially. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Close-Up of Screen We can see a little bit of glitching between characters, due to subtle timing issues Could fix by pipelining, addressing warnings from timing analyzer, etc. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Modified Keymap for Text-Entry Application Below each ASCII character in this table is the key (if any) that generates that character in the latest version of the key_decoder. Found in text_entry_v2 example The white-on-black keys are the keys in map 2 byte sequences starting with E0 or E1 Yellow keys are those that were moved to different code points in the latest version Done to assign keys to more commonly-used punctuation characters Also to generate more control codes directly via function keys. 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Further Ideas for Building on Key Decoder Write a secondary decoder that translates make-break sequences into standard ASCII characters… E.g., take as input the following event sequence… make (left shift), make (& 7), break (& 7), break (left shift) and produce as output the single character “&” Write a simple text-entry application Accept formatting characters ⌫ ↦ ↓ ↧ ↡ ↵ and translate them into appropriate cursor movements Video games, music synthesizer (piano keyboard), etc… 11/12/2018 M. Frank, EEL3705 Digital Logic, Fall 2006