ESA EJSM/JGO Radio & Plasma Wave Instrument (RPWI) Kick-off meeting 091126 Lennart Åhlén

Plasma waves Electric fields Plasma measurements Conductivities B Radio

Main box mechanics Backplane with power distribution, analog and digital interfaces Board size: 20x15cm TBC Connectors: Micro-D type Box : 21x16x12 cm average 3.2mm wall thickness for Al. Distance between Boards: 20mm

Power Voltages: +3.3V Digital interface supply +1.8V Digital DPU and FPGA core supply +-8V Analog Software current limiters (msec turn off at latch up) Common ground for all voltages Only one ground in the backplane Total power: 7W average 11W peak 100ms Instrument interfaces Digital: Differential Analog: Single ended (TBC) Satellite interfaces 2 Mbit SpaceWire Single ended (TBC)

Experimenter EMC requirements Develop the RPWI EMC requirements for the S/C by interaction during S/C design Experimenter EMC requirements All spacecraft surfaces exposed to the plasma environment shall be sufficiently conductive and grounded. < 5 kohm/sq Small surfaces differential charging potential shall not exceed +-10 V, assuming a plasma current of 5 nA/cm2 The S/C structure shall not be used as return path for power and signals except for sensor signals to avoid common impedance coupling and magnetic disturbances. Isolated receivers and balanced differential signals should be used as subsystem signal interfaces. All active wires shall be twisted with its return wire and loops on circuit boards should be minimize to reduce magnetic disturbances. The spacecraft system shall use a Distributed Single Point Grounding. Secondary power shall be grounded to structure only once in each unit / experiment. Cable shields shall be grounded to structure ground at both ends. Shields shall not be used as the return path for signal or power. Non-magnetic materials shall be used wherever possible.The use of ferro-magnetics shall be avoided wherever possible. It is recommended to use crystal oscillator controlled DC/DC converters

RPWI Grounding block diagram EMC Actions. Define acceptable satellite RE and CE levels for the frequency range DC to 45 MHz. MIL-STD-462D ECSS-E-ST-20-07C(31July2008)

Radiation protection Spot shielding should be used for all S/C external electronics Box and spot shielding should be used for the RPWI Box Use of Rad Hard components Box shielding 3.6mm 2 kg extra mass needed for 8mm box protection Action: Calculations of internal box radiation levels Radiation facilities in Uppsala Co60 1 to 10 Rad / min Free of charge Electrons 7.5 to 15 MeV high dose rate 500 Euro/h Protons 20 to 180 MeV 150 Rad/min 500Euro/h Protons max 6MeV low dose rate 100Euro/h Heavy Ions

Low and high frequency analyzers Lennart Åhlen Scientists dream receiver A downgrade is needed for the JGO receivers.

A downgrade is needed for the JGO receivers. TDA: Development of FPGA algorithms for digital analyzers to obtain high dynamic measurement range JGO Scientists dream receiver A downgrade is needed for the JGO receivers. Dynamic range: The ratio of the specified maximum signal level capability of a system to its noise level in a record of continues sampled data. What is required to fulfill the JGO since objective? Questions to be answered by the RPWI scientists. Ranges and overlap for the low and high frequency receivers? Wave-form capture? Low and High frequency data coverage? Number of parallel data channels? Type of on-board data analyzes?

Low frequency receiver Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Buffer memory for wave form capture and Burst data. Dynamic range: 80dB to ~120dB @ 100Hz bandwidth High frequency receiver Burst data signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Buffer memory for wave form capture and Burst data. Dynamic range: 70dB to ~100dB @ 10kHz bandwidth Measurement range: 70dB to ~120dB @ 10kHz bandwidth Dynamic range: 70dB to ~100dB @ 10kHz bandwidth

Under sampling high frequency receiver All high speed ADCs has a higher analog bandwidth than the maximum sampling rate. This makes it possible to build HF digital receivers by use of under-sampling. Under-sampling design approach is replacing mixer-based heterodyne receivers. Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Principle of under sampling

Dual 1 0 -1 I/Q Mixer including SH Conventional mixer using high speed analog switches. Antenna impedance measurements Net work analyzer S11 type measurements Impedance antenna to plasma vs. frequency Useful for side-by-side antenna comparisons

RA-PWI, RWI and LP-PWI Preamplifiers Lennart Åhlen

LP_PWI Preamplifier Specifications: Switchable E-field / Density 100mW power consumption 500kRad Radiation hardend Positive feed back current generator E-field: DC-300Hz +-100V input range DC to 3MHz small signal bandwidth Better than 10^9 input resistance 1nA – 1uA Current Bias range 16 nV/sqr(Hz) noise Density: DC to 10kHz bandwidth 10pA to 1uA input current range +-100V Voltage Bias range Mission heritage:. Viking: E-field / Density Rosetta: E-field / Density Freja: E-field / Density Cluster: E-field / Density Astrid: E-field / Density Swarm: Density Cassini: Density New development: Find new low noise Rad hard operational amplifiers Develop a MEMS chip including nano-switches and amplifiers

RA_PWI and RWI Preamplifier FET follower or FET input negative feed back amplifier ? High distortion Limited output range Low power Simple Low distortion Medium power Complex Specifications: 1kHz to 50MHz Bandwidth 2 nV/sqr(Hz) noise +-1V input range 100mW power consumption

Low Voltage Power Supply (LVPS) Göran Olsson Royal Institute of Technology (KTH) Space and Plasma Physics

LVPS CONTROL & MONITORING LVPS IN RPWI JGO LFA + AM +8V / -8V 3.3V 1.8V LVPS-A +8V / -8V SCM 3.3V SCM PREAMP 1.8V +8V 3.3V DPU -8V 1.8V CEB BACKPLANE 3.3V LVPS CONTROL & MONITORING 1.8V LP-PWI +8V / -8V 3.3V LP-PWI Preamps 1.8V LVPS-B TBD +8V / -8V RWI RA-PWI HFA 3.3V RWI Preamps 1.8V RA-PWI Preamp Clock, Control, Data and Emergency Power-Off, A + B

LVPS Requirements Functional: DC power to all RPWI instruments: ±8V +3.3V, +1.8 V from 25-36 V input, nominal total power output: ~10 W CEB Form Fit: PCB Dimensions 200x 150 x 1.6 mm Component height 12 mm upper side, 3 mm lower side Backplane connector 160 pin, 3 row Airborn WG series Mass 300 g Primary to secondary isolation Temperature range: -30 °C to +50 °C operating Redundant DC/DC converters and digital controllers TBD Power Switching: 5 instruments having two to four supply voltages Voltage and Current Monitoring Overcurrent Tripping; Limits under software control Temperature Monitoring: DC/DC converter and SCM sensor Performance: No-load Power (Including DC/DC converter, controller, monitoring and switches): 1.1 W Differential Efficiency: 82% Output Deviation: ±5% from nominal including all effects Output Ripple: < 5 mVrms

CDPU-A Ctrl: Clock, Command, Data, EPO LVPS Block Diagram From SC 28V DC/DC Converter A 1.8, 3.3 V Voltage And Current Monitors (4) CEB BPLN DPU Common-Mode Filter DC/DC Converter B 1.8, 3.3 V From SC 28V Common-Mode Filter Power Switches (9 Instruments) Voltage and Current Monitors (24) 1.8, 3.3, ±8 V Common Bus Redundant TBD DC/DC Converters and Controllers chained with the DPU Unused chain is a cold spare Common power bus for all instruments. Design to minimize risk of single point failures here. What if both chain A and B are powered? Must be survivable, but no functional requirement. - No mutual interlock implemented. Subject of further study. 1.8 V is regulated to 1.5 V locally on each subsystem Power switches have turn-on ramping Emergency Power-Off Housekeeping From SCM Thermistor Controller A FPGA CDPU-A Ctrl: Clock, Command, Data, EPO Controller B FPGA

DC/DC Converter A/B Primary Secondary Main Transformer Shielded Secondary Shielded Main Transformer Input: 27- 36 V First Stage Second Stage Outputs: +1.8 V, 1.1 A +3.3 V, 1.1 A +8 V, 350 mA -8 V, 300 mA Pulse-Width Modulator ‘Forward’ Converter 420 kHz EMI Filter Synchronous Rectifiers 13-14 V DC Inrush current limiter Output Filters Transformer Driver - Switchmode Regulator Controller 50mΩ + Internal: ±15 V Regulated input voltage to Transformer Driver Current positive feedback: Counterbalances losses in driver transistors, transformer and rectifiers. Primary to Secondary Isolation Double Shielding Push-Pull Full-Wave 210 kHz Full-Wave Rectification LC Pi Filters No Feedback from Secondary Two-stage Conversion: Excellent input and load regulation Low noise Low output cross-regulation Slightly lower efficiency

Digital Controller A/B Power Switch Control (9) FPGA 3.3 V Linear Regulators: 1.5 V 2.5 V HK Control (ADC, Mux, Gain Switch) DC/DC A/B Instrument Power Control Housekeeping Control with Storage and Readout Overcurrent Tripping, limits under software control IVM: Actel ProASIC3 A3P250 FM: Actel RTSX72 LVDS CDPU A/B Housekeeping ADC Data System clock derived from the CDPU interface clock: 1.048 MHz If three consecutive samples (~15 ms) exceed the limit ► All voltages turned off for the affected instrument

Impacted on the Moon as planned on September 3, 2006. Design Heritage DC/DC Converter, Housekeeping System and Stepper Motor Controller for EMMA, a plasma payload on the Swedish Astrid-2 satellite, launched December 10, 1998. Dimensions 177 x 134 x 16 mm. DC/DC design power 10 W. COTS components. This design has many features in common with the MMS LVPS. DC/DC Converter for SPEDE, a plasma payload on the SMART-1 ESA Lunar Orbiter, launched 2003. Dimensions 71 x 44 x 11 mm. Design power is a mere 1.2 W. Impacted on the Moon as planned on September 3, 2006. LVPS IVM on the UNH lab bench with co-delivered dummy load board

Walter Puccio & Reine Gill RPWI DPU Walter Puccio & Reine Gill

CPU 32-bit Sparc V8 Aeroflex/Gaisler RTAX Actel 24MHz LEON3-FT 0.5-0.3W @24MHz 20 MIPS and 4 MFLOPS 3 x Spacewire links CQFP 352 or CCGA 624 (Actel RTAX 2000S) 300kRad, Fault Aeroflex/Gaisler UT699 ASIC 66MHz LEON3-FT 4.0W+ @66MHz (?) 52.8 MIPS 11 MFLOP 4x Spacewire links CQFP 352 or BGA 484 (32g) 300kRad ATMEL RH ASIC 100MHz LEON2-FT 1.0W @100MHz 86 MIPS and 23 MFLOPS MQFPF 256 or MCGA 349 (9g)

CPU & Memory LEON2FT Actel or RTAX LEON3FT 4KB Boot PROM Analog Monitoring & Power CTRL Spacewire link to S/C ~2Mbit/s 8-12 MByte SRAM (EDAC) LEON2FT or LEON3FT Actel RTAX 64MByte FLASH 20-86 MIPS 4-23 MFLOP 4KB Boot PROM Serial links with simple protocol to instrument FPGAs

Algorithm dataflow, decimation and processing Instrument ADCs raw data Instrument FPGAs with optional data processing and decimation Serial links DPU FPGA with optional data processing and decimation CPU with optional data processing and decimation Spacewire to S/C

RTOS RTEMS (preferable) Interupt driven (no scheduling) RT Linux Proven flight software on LEON CPUs Multi-tasking Interupt driven (no scheduling) Very small footprint RT Linux Open source

Mission heritage Viking (software) Freja (sensor, hardware and software) Cassini (sensor, hardware and software) Astrid 1&2 (sensor, hardware and software) Munin (S/C, sensor, hardware and software) Rosetta (sensor, hardware and software) Swarm (sensor, hardware and software) RTEMS on LEON2 BepiColombo (sensor, hardware)