CMOS VLSI Design Chapter 2: MOSFET Theory This work is protected by Canadian copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning. Dissemination or sale of any part of this work (including on the Internet) will destroy the integrity of the work and is not permitted. The copyright holder grants permission to instructors who have adopted the textbook accompanying this work to post this material online only if the use of the website is restricted by access codes to students in the instructor's class that is using the textbook and provided the reproduced material bears this copyright notice. slides from David Harris adapted by Duncan Elliott Textbook: CMOS VLSI Design - A Circuits and Design Perspective, 4th Edition, N.H.E. Weste & D. Harris Ch 2. MOS Theory

Review Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance Ch 2. MOS Theory

Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (DV/Dt) -> Dt = (C/I) DV Capacitance and current determine speed Ch 2. MOS Theory

MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion Ch 2. MOS Theory

Terminal Voltages Mode of operation depends on Vg, Vd, Vs Vgs = Vg – Vs Vgd = Vg – Vd Vds = Vd – Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds  0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation (Pinchoff) Ch 2. MOS Theory

nMOS Cutoff No channel Ids ≈ 0 Ch 2. MOS Theory

nMOS Linear Channel forms Current flows from d to s e- from s to d Ids increases with Vds Similar to linear resistor Ch 2. MOS Theory

nMOS Saturation/ Pinchoff Channel pinches off Ids independent of Vds We say current saturates Similar to current source Ch 2. MOS Theory

I-V Characteristics In Linear region, Ids depends on How much charge is in the channel? How fast is the charge moving? Ch 2. MOS Theory

Channel Charge MOS structure looks like parallel plate capacitor while operating in inversions Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt Cox = eox / tox Ch 2. MOS Theory

Carrier velocity Charge is carried by e- Electrons are propelled by the lateral electric field between source and drain E = Vds/L Carrier velocity v proportional to lateral E-field v = mE m called mobility Time for carrier to cross channel: t = L / v Ch 2. MOS Theory

nMOS Linear I-V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross Ch 2. MOS Theory

nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current Ch 2. MOS Theory

nMOS I-V Summary Shockley 1st order transistor models Ch 2. MOS Theory

Example Using a 0.6 mm process From AMI Semiconductor tox = 100 Å m = 350 cm2/V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 l Ch 2. MOS Theory

pMOS I-V All dopings and voltages are inverted for pMOS Source is the more positive terminal Mobility mp is determined by holes Typically 2-3x lower than that of electrons mn 120 cm2/V•s in AMI 0.6 mm process Thus pMOS must be wider to provide same current In this class, assume mn / mp = 2 Ch 2. MOS Theory

Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion Ch 2. MOS Theory

Gate Capacitance Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm Ch 2. MOS Theory

Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff ½ Cg for uncontacted Varies with process Ch 2. MOS Theory

Outline Nonideal Transistor Behavior High Field Effects Mobility Degradation Velocity Saturation Channel Length Modulation Threshold Voltage Effects Body Effect Drain-Induced Barrier Lowering Short Channel Effect Leakage Subthreshold Leakage Gate Leakage Junction Leakage Process and Environmental Variations Ch 2. MOS Theory

Ideal Transistor I-V Shockley long-channel transistor models Ch 2. MOS Theory

Need more accuracy? "The Berkeley Short Channel IGFET (insulated gate field-effect transistor) Model, BSIM, is a SPICE model for n- and p-channel MOS transistors.... " [CMOS, Baker, Li, Boyce] BSIM1 L >= 1 micron; BSIM2, BSIM3 below that BSIM2 39 parameters BSIM3 75 parameters Automated extraction of process parameters popular Ch 2. MOS Theory

Ideal vs. Simulated nMOS I-V Plot 65 nm IBM process, VDD = 1.0 V Ch 2. MOS Theory

ON and OFF Current Ion = Ids @ Vgs = Vds = VDD Saturation Ioff = Ids @ Vgs = 0, Vds = VDD Cutoff Ch 2. MOS Theory

Electric Fields Effects Vertical electric field: Evert = Vgs / tox Attracts carriers into channel Long channel: Qchannel  Evert Lateral electric field: Elat = Vds / L Accelerates carriers from drain to source Long channel: v = mElat Ch 2. MOS Theory

Walking Analogy Many students are around at period change At high Vds, you scatter off other students, fall down, get up Velocity saturation Don’t confuse this with the saturation region Vgs is a wind blowing you against the glass (SiO2) wall At high Vgs, you are buffeted against the wall Mobility degradation Ch 2. MOS Theory

Mobility Degradation High Evert effectively reduces mobility Collisions with oxide interface Ch 2. MOS Theory

Velocity Saturation At high Elat, carrier velocity rolls off Carriers scatter off atoms in silicon lattice Velocity reaches vsat Electrons: 107 cm/s Holes: 8 x 106 cm/s Better model Ch 2. MOS Theory

Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L – Ld Shorter Leff gives more current Ids increases with Vds Even in saturation Ch 2. MOS Theory

Chan Length Mod I-V l = channel length modulation coefficient not feature size Empirically fit to I-V characteristics Ch 2. MOS Theory

Threshold Voltage Effects Vt is Vgs for which the channel starts to invert Ideal models assumed Vt is constant Really depends (weakly) on almost everything else: Body voltage: Body Effect Drain voltage: Drain-Induced Barrier Lowering Channel length: Short Channel Effect Ch 2. MOS Theory

Body Effect Body is a fourth transistor terminal Vsb affects the charge required to invert the channel Increasing Vs or decreasing Vb increases Vt fs = surface potential at threshold Depends on doping level NA And intrinsic carrier concentration ni g = body effect coefficient Ch 2. MOS Theory

Body Effect Cont. For small source-to-body voltage, treat as linear Ch 2. MOS Theory

DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering Drain voltage also affect Vt High drain voltage causes current to increase. Ch 2. MOS Theory

Short Channel Effect In small transistors, source/drain depletion regions extend into the channel Impacts the amount of charge required to invert the channel And thus makes Vt a function of channel length Short channel effect: Vt increases with L Some processes exhibit a reverse short channel effect in which Vt decreases with L Ch 2. MOS Theory

Leakage What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff Ch 2. MOS Theory

Leakage Sources Subthreshold conduction Transistors can’t abruptly turn ON or OFF Dominant source in contemporary transistors Gate leakage Tunneling through ultrathin gate dielectric Junction leakage Reverse-biased PN junction diode current Ch 2. MOS Theory

Subthreshold Leakage Subthreshold leakage exponential with Vgs  is process dependent typically 1.3-1.7 Rewrite relative to Ioff on log scale S ≈ 100 mV/decade @ room temperature Ch 2. MOS Theory

Gate Leakage Carriers tunnel thorough very thin gate oxides Exponentially sensitive to tox and VDD A and B are tech constants Greater for electrons So nMOS gates leak more Negligible for older processes (tox > 20 Å) Critically important at 65 nm and below (tox ≈ 10.5 Å) From [Song01] Ch 2. MOS Theory

Junction Leakage Reverse-biased p-n junctions have some leakage Ordinary diode leakage Band-to-band tunneling (BTBT) Gate-induced drain leakage (GIDL) Ch 2. MOS Theory

Diode Leakage Reverse-biased p-n junctions have some leakage At any significant negative diode voltage, ID = -Is Is depends on doping levels And area and perimeter of diffusion regions Typically < 1 fA/mm2 (negligible) Ch 2. MOS Theory

Band-to-Band Tunneling Tunneling across heavily doped p-n junctions Especially sidewall between drain & channel when halo doping is used to increase Vt Increases junction leakage to significant levels Xj: sidewall junction depth Eg: bandgap voltage A, B: tech constants Ch 2. MOS Theory

Gate-Induced Drain Leakage Occurs at overlap between gate and drain Most pronounced when drain is at VDD, gate is at a negative voltage Thwarts efforts to reduce subthreshold leakage using a negative gate voltage Ch 2. MOS Theory

Temperature Sensitivity Increasing temperature Reduces mobility Reduces Vt ION decreases with temperature IOFF increases with temperature Ch 2. MOS Theory

So What? So what if transistors are not ideal? They still behave like switches. But these effects matter for… Supply voltage choice Logical effort Quiescent power consumption Pass transistors Temperature of operation Ch 2. MOS Theory

Parameter Variation Transistors have uncertainty in parameters Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values Fast (F) Leff: short Vt: low tox: thin Slow (S): opposite Not all parameters are independent for nMOS and pMOS Ch 2. MOS Theory

Environmental Variation VDD and T also vary in time and space Fast: VDD: high T: low Corner Voltage Temperature F 1.98 0 C T 1.8 70 C S 1.62 125 C Ch 2. MOS Theory

Process Corners Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. Describe corner with four letters (T, F, S) nMOS speed pMOS speed Voltage Temperature Ch 2. MOS Theory

Important Corners Some critical simulation corners include Purpose nMOS pMOS VDD Temp Cycle time S Power F Subthreshold leakage Ch 2. MOS Theory

Extra Notes/ Review Ch 2. MOS Theory

DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 In between, Vout depends on transistor size and current By KCL, must settle such that Idsn = |Idsp| We could solve equations But graphical solution gives more insight Ch 2. MOS Theory

Transistor Operation Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in Cutoff? Linear? Saturation? Ch 2. MOS Theory

Operating Regions Region nMOS pMOS A Cutoff Linear B Saturation C D E Ch 2. MOS Theory

Inverter Load Lines Vin = 1V IDn (A) Vin = 1.5V Vin = 2V Vin = 0.5V X 10-4 PMOS NMOS Vin = 0V Vin = 2.5V Vin = 0.5V Vin = 2.0V Vin = 1V Vin = 1.5V IDn (A) Vin = 1.5V Vin = 2V Vin = 0.5V Vin = 1.0V Vin = 1.0V Vin = 1.5V Vin = 0.5V dc points located at the intersection of the corresponding load lines Note all operating points are located either at the high or low output levels Vin = 2.0V Vin = 2.5V Vin = 0V Vout (V) 0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V Ch 2. MOS Theory

Beta Ratio If bp / bn  1, switching point will move from VDD/2 Called skewed gate Other gates: collapse into equivalent inverter Ch 2. MOS Theory

Noise Margins How much noise can a gate input see before it does not recognize the input? Ch 2. MOS Theory

Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic VOH VM VOL VIL VIH Ch 2. MOS Theory

Not shown: rise and fall times Ch 2. MOS Theory

Ch 2. MOS Theory

Ch 2. MOS Theory

Ch 2. MOS Theory

Ch 2. MOS Theory

Transmission Gate Equivalent Resistance For high VDD, assume R doubles for unfavoured level (NMOS passing “1”, PMOS “0”) Poor assumption as VDD shrinks faster than VT Ch 2. MOS Theory

Ch 2. MOS Theory

Ch 2. MOS Theory

Ch 2. MOS Theory