A Fast Binary Front - End using a Novel Current-Mode Technique for the LHCb Muon Detector CARIOCA D. Moraes, F. Anghinolfi, P. Deval, P. Jarron, W. Riegler, A. Rivetti, B. Schmidt 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes

LHCb Muon System Total number of MWPCs: ~600 125K readout channels 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 5 Muon stations, which provide  identification and Level-0  trigger formation Each station must have an efficiency > 99%, within 20ns time window time resolution of 3.5ns for a double gap MWPC Total number of MWPCs: ~600 125K readout channels

LHCb Muon System FE-Electronics 3 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 FE-chip specifications: Peaking time ~10ns RIN: < 50  CDetector: 10-200pF Polarities: +/- Rate: up to 1MHz Dead time: < 50ns Dose: up to 1Mrad Sensitivity: ~8mV/fC (@Cdet =0) Low noise . . .  No existing chip fully satisfies our requirements Inefficiency due to ASD pulse-width

What is CARIOCA ? 8-channel Amplifier Discriminator chip 4 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 2x2mm2 Low gain : MWPC of the LHCb Muon system High gain : Silicon strip detectors 8-channel Amplifier Discriminator chip Technology: 0.25m CMOS Very fast and Low noise current mode Preamplifier, designed in two versions:

Low Gain Circuit Description 5 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Each channel is formed by a current mode preamplifier, a three-stage discriminator and a LVDS driver 5

Low Gain Circuit Description 6 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 DC chain, which allows high counting rate readout without baseline shift effects Voltage supply: 2.5V single rail Only one signal return path (ground) to be more robust on power supply rejection Independent biasing and threshold circuit on each channel, which may avoid crosstalk between channels Optimized for detector capacitances up to 20pF, but it is working up to 120pF 6

Preamplifier Description 7 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 n-channel structure with an active feedback and large input transistor - W/L=1600m/0.7 m gm = 30mS Idrain = 2mA, defined by a p-channel cascode current source RIN ~ 10 for medium frequencies 7

Discriminator Description 8 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Three stages discriminator: current discriminator voltage sensing amplifier buffer, followed by a LVDS driver Baseline restoration based on DC loop circuit (not shown) 8

Measurement Results 9 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Examples of analog and digital signals @ Cdet.=15pF Input charge from 10fC to 40fC Input charge from 60fC to 100fC 9

Measurement Results Peaking time tpeak = 14ns @ Cdet.= 0pF for a 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Peaking time Simulation = 12.1ns + 0.07Cdet. Measurement = 14.0ns + 0.07Cdet. tpeak = 14ns @ Cdet.= 0pF for a  input with trise = 5ns If  input of 1ns trise is considered, a 2ns reduction on the peaking time can be obtained weak dependence on Cdet. Simulated tpeak for the preamplifier alone is about 8ns 10

Measurement Results Sensitivity Preamplifier gain ~ 8mV/fC 11 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Sensitivity Preamplifier gain ~ 8mV/fC Current gain = 6 Good uniformity up to Cdet.= 120pF Excellent agreement with the simulation Simulation Measurement

Measurement Results Noise x CDetector Measurements performed with 12 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Noise x CDetector Calculation Measurement Measurements performed with Idrain= 2mA  gm = 30mS ENCP = 450e- Noise slope 37.4e-/pF for Cdet. < 50pF 54.4e-/pF for Cdet. > 50pF For RC-CR filters of 25ns the noise slope is ~ 27e-/pF for low and 40.7e-/pF for high Cdet.

Noise Calculation ENCP = 416e- noise slope = 35.9e-/pF vin = 0.7nV/Hz 13 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Brief noise calculation was performed considering a weighting function with a bipolar shape (V. Radeka, Ann. Rev. Nucl. Part. Sci. 1988, 217-277.) Estimated noise characteristics of 0.25CMOS technology n = 1.4,  = 0.6 and Af = 410-14 V2/Hz ENCP = 416e- noise slope = 35.9e-/pF vin = 0.7nV/Hz ENC1/f = 1.2e-/pF

Conclusions Low gain version of CARIOCA showed a good agreement 14 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Low gain version of CARIOCA showed a good agreement with the expected results. Total power consumption of 12mW/channel, including discriminator and LVDS driver. Noise measurement indicates an excellent performance of the current mode feedback and agrees with noise calculations based on 0.25CMOS technology parameters.

Future Plans Produce a new prototype with 14-channels to study channel 15 11-15 Sept. 2000 6th Workshop on Electronics for LHC Experiments D. Moraes RD49 Produce a new prototype with 14-channels to study channel uniformity and crosstalk. An improved chip with shaper and baseline restoration circuits is under development. The final goal is a chip optimized for detector capacitances up to 200pF with both polarities readout, a faster discriminator and a logic circuit necessary for the trigger system.