MODEM REGISTER VERIFICATION

Register name: MOD_DEVID (RO) Register Address: 0x600, 0x602 Testcase ID: mod_reg_mod_dev_id.c Purpose: To check if device ID is updated in the register. Description: Read register and compare with expected value. Address: 0x600 – Expected data: 0x01 Address: 0x602 – Expected data: 0x00 Expected outcome: Time 12.19us -> Register address: 0x600 (mif_addr), Read data: 0x01 (mif_rd_data) Time 15.44us -> Register address: 0x602 (mif_addr), Read data: 0x00 (mif_rd_data)

Register name: RSSI_VAL (RO) Register Address: 0x604 Testcase ID: mod_reg_rssi.c Purpose: To check if measured RSSI value is updated in the register. Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Read register and compare with expected value at BT2 side. Address: 0x604 – Expected data: 0xA9 Expected outcome: Time: 13482.7us -> Register Address: 0x604 (mif_addr), Read data: 0xA9 (mif_rd_data)

Understanding: RSSI value is calculated based on AGC gain and average power. AGC gain is calculated based on LNA gain, Block 1 (Mixer) gain, Block 2 (VGA) gain. Since the received signal is attenuated in the channel model, the AGC gain adjusts the received signal to a suitable power level.

Register name: TXFUNC_CNTL_LW (RW) – BT_SEL bit Register Address: 0x608 Testcase ID: mod_reg_txfc_ctrl_bt_sel.c Purpose: Test if the IUT works with the selected BT product configuration 0 - Configure BT product 0.5 (Default) 1 - Configure BT product 0.55 Description: Set attenuation value = -85 dBm at BT1 side. Set frequency offset and frequency drift to zero. Write register with value 0x0000 ( BT = 0.5) or 0x0008 (BT = 0.55).

Case 1: BT = 0.5 (iTxBTsel: 1’b0) Contd.. Case 1: BT = 0.5 (iTxBTsel: 1’b0) Expected outcome: Time: 22.74 us -> Register Address: 0x608 (mif_addr), Write data: 0x0000 (mif_wr_data) Time: 1063.57 us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne_1

Case 2: BT = 0.55 (iTxBTsel = 1’b1) Contd.. Case 2: BT = 0.55 (iTxBTsel = 1’b1) Expected outcome: Time:404.03us -> Register Address: 0x608 (mif_addr), Write enable: 1’b1 (wr_en_signal), Write data: 0x0008 (mif_wr_data) Time:404.10us -> Register Address: 0x608 (mif_addr), Read data: 0x0008 (mif_rd_data) Time: 1063.63 us -> Output signal: oCoeffPlusOne1 = wCoeffPlusOne55_1

BT_SEL = 0.55 BT_SEL = 0.5 Understanding: 1. For BT= 0.5, the pulse shaping the symbol spreads over 2 bit period duration (Time = 378.3125us for 1 packet). 2. For BT = 0.55, the symbol spread will be less than 2 bit period duration (Time = 378.25us for 1 packet).

Register name: RXFUNC_CNTL_LW (RW) - EL_FULL_PKT_TRK, EL_SLOW_TRK_ENB, EL_SAMP_ADJ, EL_CTRL, RSSI_THRESHOLD bits Register Address: 0x61C Testcase ID: mod_reg_el_func_ctrl.c Purpose: To check early late functionality: EL_FULL_PKT_TRK - Early late tracking for full packet. EL_SLOW_TRK_ENB - Early late slow tracking for payload. EL_SAMP_ADJ - Early late sampling point adjustment. EL_CTRL - Early late sum comparison. RSSI_THRESHOLD - RSSI detection threshold for early late adjustment. Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FCA to enable the above mentioned register bits. Write RXFUNC_CTRL register with value 0x7FFC to disable the above mentioned register bits. Write RSSI_THRESHOLD with value 0x3F and 0x7F to check if the threshold value can be set to all bit range.

Case 2: Function Disable Contd.. Case 1: Function Enable Expected outcome: Time: 419.72 us -> Register Address: 0x61C (mif_addr), Write data: 0x3FCA (mif_wr_data), iElTrkFullPkt: 1’b1, iElSlwTrkEnb: 1’b0, iElSampAdj: 1’b0, iElCtrl: 1’b0, iModCntrlRssiThres[6:0]: 7’h3F Case 2: Function Disable Time: 419.72 us -> Register Address: 0x61C (mif_addr), Write data: 0x7FFC (mif_wr_data), iElTrkFullPkt: 1’b0, iElSlwTrkEnb: 1’b1, iElSampAdj: 1’b1, iElCtrl: 1’b1, iModCntrlRssiThres[6:0]: 7’h7F

2. EL_SLOW_TRK_ENB: Enables/disables slow tracking Understanding: EL_CTRL: Controls the Early and Late sum comparison with threshold value. EL_CTRL = 1, Threshold met signal will be high when both Early and Late sum are greater than Threshold. EL_CTRL = 0, Threshold met signal will be high when either Early sum or Late sum is greater than Threshold. When Threshold met signal is high, the forward and backward sample adjustment indication will be updated and samples will be adjusted based on the indication. 2. EL_SLOW_TRK_ENB: Enables/disables slow tracking EL_SLOW_TRK_ENB =1 , slow tracking will be enabled and samples will be adjusted after Access address match. Sample adjustment happens when the slow track counter is equal to the slow track threshold. EL_SLOW_TRK_ENB =0 , slow tracking will be disabled and samples will be adjusted before Access address match. 3. EL_FULL_PKT_TRK: Enables/disables Full packet tracking EL_FULL_PKT_TRK =0 , full packet tracking will be enabled and samples will be adjusted for payload. EL_FULL_PKT_TRK =1 , full packet tracking will be disabled and samples will be adjusted till preamble (not for payload). Contd..

Contd.. 4. EL_SAMP_ADJ: Enables/Disables the Early Late Sampling point adjustment based on Early late and matched filter average threshold. EL_SAMP_ADJ = 0, Early Late Sampling point adjustment will be based only on Early late threshold met (one packet loss). EL_SAMP_ADJ = 1, Early Late Sampling point adjustment will be based on Early late threshold met and matched filter average threshold (More effective - all packet received). 5. RSSI_THRESHOLD: RSSI value should be above the configured threshold to enable early late adjustment in the modem. If threshold value is not configured with correct value then Early late adjustment operation will not happen.(Packet loss)

Register name: RXFUNC_CNTL_LW (RW) – NORM_PH_CTRL bit Contd.. Register name: RXFUNC_CNTL_LW (RW) – NORM_PH_CTRL bit Register Address: 0x61C Testcase ID: mod_reg_norm_ph_ctrl.c Purpose: To check the Normalizer input data selection 0 - Selects the input data 1 - Selects the registered input data Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FFF to select the registered input data. Write RXFUNC_CTRL register with value 0x3FBF to select the input data.

Case 1: NORM_PH_CTRL bit enabled Contd.. Case 1: NORM_PH_CTRL bit enabled Expected outcome: Time:419.50us -> Register Address: 0x61C (mif_addr), Write data: 0x3FFF (mif_wr_data), iNormPhaseCtrl: 1’b1 Time: 534.35 us -> Output signal: wNormInPhase_sel = NormInPhase_q for iNormPhaseCtrl : 1’b1

Case 2: NORM_PH_CTRL bit disabled Contd.. Case 2: NORM_PH_CTRL bit disabled Expected outcome: Time:419.72us -> Register Address: 0x61C (mif_addr), Write data: 0x3FBF (mif_wr_data), iNormPhaseCtrl: 1’b0 Time: 534.28 us -> Output signal: wNormInPhase_sel = iNormInPhase for iNormPhaseCtrl : 1’b0 Understanding: NORM_PH_CTRL: Normalizer input data selection bit. NORM_PH_CTRL = 0, select the incoming input data NORM_PH_CTRL = 1, select the registered input data. To synchronize with the clock.

Register name: RXFUNC_CNTL_LW (RW) – FREQ_CHCK_SUM bit Register Address: 0x61C Testcase ID: mod_reg_chksum_enb.c Purpose: To check enabling/disabling of frequency check sum feature 0 - Disable 1 - Enable Description: Set attenuation value = -85 dBm at BT1 side. Write RXFUNC_CTRL register with value 0x3FFF to enable the frequency check sum feature. Write RXFUNC_CTRL register with value 0x3F7F to disable the frequency check sum feature.

Case 1: FREQ_CHCK_SUM bit enabled Expected outcome: Time: 419.72us -> Register Address: 0x61C (mif_addr), Write data: 0x3FFF (mif_wr_data), iFreqCheckSumEnb: 1’b1 Time: 419.72us -> Output signal: wFreqCheckSumFail = 1’b1 or 1’b0 based on the frequency check sum calculation for iFreqCheckSumEnb : 1’b1

Case 2: FREQ_CHCK_SUM bit disabled Expected outcome: Time:419.58us -> Register Address: 0x61C (mif_addr), Write data: 0x3F7F (mif_wr_data), iFreqCheckSumEnb: 1’b0 Time:49.28 us -> Output signal: wFreqCheckSumFail = 1’b0 for iFreqCheckSumEnb: 1’b0 Understanding: 1. FREQ_CHCK_SUM : Enables/disables the frequency check sum feature FREQ_CHCK_SUM = 1, Checksum fail signal will become high when the estimated checksum value is less than threshold value. Which is used to avoid the frequency correction for false preamble detection. FREQ_CHCK_SUM = 0, Checksum fail signal will become low.

Register name: RXFUNC_CNTL_UW (RW) – ADJ_CORR_VAL, DELTA_THRES_VAL bit Register Address: 0x61E Testcase ID: mod_reg_corr_delta_th.c Purpose: 1. To check read and write operation of adjustment of correlation value from Frequency Offset Estimation module which is sent to Early Late module. 2. To check read and write operation of Delta threshold value which adjusts the Early Late Samples. Description: Set attenuation value = -85 dBm at BT1 side. Write and read RXFUNC_CTRL_UW register with value 0xFFFF (ADJ_CORR_VAL = 0x3F and DELTA_THRES_VAL=0x3FF which is the maximum value for both the bits). Write and Read RXFUNC_CTRL_UW register with value 0x0001 (ADJ_CORR_VAL = 0x00 and DELTA_THRES_VAL=0x001 which is the minimum value for both the bits).

Case 1: Maximum Value Case 2: Minimum Value Expected outcome: Contd.. Expected outcome: Time:419.66us -> Register Address: 0x61E(mif_addr), Write Enable: 1’b1(wr_en_signal), Write data: 0xFFFF (mif_wr_data). Time:419.72us -> Register Address: 0x61E(mif_addr), Read data: 0xFFFF(mif_rd_data), iDeltaThres: 10’h3FF, iAdjCorrVal: 6’h3F. Case 2: Minimum Value Expected outcome: Time:419.66us -> Register Address: 0x61E(mif_addr), Write Enable: 1’b1(wr_en_signal), Write data: 0x0001 (mif_wr_data). Time:419.72us -> Register Address: 0x61E(mif_addr), Read data: 0x0001 (mif_rd_data), iDeltaThres: 10’h001, iAdjCorrVal: 6’h00. Note: 1. Minimum and Maximum values will remain same for Frequency offset = 300KHz and Frequency Drift = 100KHz. 2. When the register value is set less than the minimum value packet reception will be degraded.

Contd.. Understanding: ADJ_CORR_VAL: Correlation value will be adjusted based on the configured value. Configured value will adjust the peak position in Frequency offset estimation module. Adjusted peak position will be used in Early Late module to calculate the sample count which in turn is used to adjust the samples. 2. DELTA_THRES_VAL: Delta threshold value which is used to adjust the Early Late Samples. Early – Late i.e delta value which is calculated based on EarlySum and LateSum must be always greater than or equal to the configured threshold value. If the calculated delta value is less than the configured threshold value then sample adjustment will get affected due to which there will be degradation in the packet reception.

Register name: MOD_CNTL_LW (RW) – SM_CNTRL bit and MOD_OPER_LW – SM_ENB bit Register Address: 0x624, 0x628 Testcase ID: mod_reg_sm_cntrl_en.c Purpose: 1. To check the configured bit controls the sleep mode operation from modem (SM_CNTRL) 2. To check the configured bit enables/disables the sleep mode operation (SM_ENB). Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_CNTL_LW register with value 0x0008 to control the sleep mode operation from modem. Write and read MOD_OPER_LW register with value 0x0004 to enable the sleep mode operation. Write and read MOD_OPER_LW register with value 0x0000 to disable the sleep mode operation.

Case 1: SM_CNTRL and SM_ENB disabled Contd.. Expected outcome: Time:422.66us -> wRegBankSmCntl:1’b0, wSleepEnb:1’b0, wTxClkEnb: 1’b1, wRxClkEnb:1’b1, wTxRxClkEnb:1’b1 Expected outcome: Time:61.03us -> wRegBankSmCntl:1’b1 Time:422.66us -> wSleepEnb:1’b1, wTxClkEnb: 1’b0, wRxClkEnb:1’b0, wTxRxClkEnb:1’b0 Understanding: When sleep mode operation is enabled Tx and Rx clock will be disabled and device will enter into sleep mode operation (No transmission or reception of packets).

Register name: MOD_OPER_LW – DYN_PWR_CNTRL bit Register Address: 0x628 Testcase ID: mod_reg_dyn_pwr_cntrl.c Purpose: To check the configured bit enables/disables the dynamic power control. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0008 to enable the dynamic power. Write and read MOD_OPER_LW register with value 0x0000 to disable the dynamic power..

Case 1: DYN_PWR_CNTRL enabled Contd.. Expected outcome: Time = 533.78us -> wRegBankDynPwrCntl:1’b1, wTxClkEnb: 1’b1, wRxClkEnb:1’b1, wTxRxClkEnb:1’b1 Time =1452.56 us -> wRegBankDynPwrCntl:1’b1, wTxClkEnb: 1’b0, wRxClkEnb:1’b0, wTxRxClkEnb:1’b0 Case 2: DYN_PWR_CNTRL disabled Expected outcome: Time = 533.78us -> wRegBankDynPwrCntl:1’b0, wTxClkEnb: 1’b1, wRxClkEnb:1’b1, wTxRxClkEnb:1’b1 Time =1452.56 us -> wRegBankDynPwrCntl:1’b0, wTxClkEnb: 1’b1, wRxClkEnb:1’b1, wTxRxClkEnb:1’b1 Understanding: When dynamic power control is enabled, it will disable the Tx and Rx clock (only when Tx and Rx operation are idle). When dynamic power control is disabled. Tx and Rx clock will be always high even when the Tx and Rx operation are idle.

Register name: MOD_OPER_LW –RxClkCtrl1 bit Register Address: 0x628 Testcase ID: mod_reg_rx_clk_cntrl.c Purpose: To check the configured bit control the clock start stop timing for preamble search module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Preamble search module.(clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0010 to disable the clock start stop timing for Preamble search module. (clock will be on for entire RX)

Case 1: RxClkCtrl1 disabled Contd.. Case 1: RxClkCtrl1 disabled Expected outcome: Time = 537.101us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b1, wModCntrlPreSrchClkG:1’b1 Time =1115.85 us -> wRegBankRxClkCtrl1:1’b0, rRxClkEnb2: 1’b0, wModCntrlPreSrchClkG:1’b0 Case 2: RxClkCtrl1 enabled Expected outcome: Time = 419.97us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, wModCntrlPreSrchClkG:1’b1 Time =1115.29 us -> wRegBankRxClkCtrl1:1’b1, rRxClkEnb2: 1’b1, wModCntrlPreSrchClkG:1’b1 Understanding: Clock will be selected based on the configured bit.

Register name: MOD_OPER_LW – FreqOffClkCtrl bit Register Address: 0x628 Testcase ID: mod_reg_freq_off_clk_ctrl.c Purpose: To check the configured bit control the clock start stop timing for frequency offset estimation module. 0 – Clk ON from RSSI Detection to Access address match 1 – Clk ON during entire RX. Description: Set attenuation value = -85 dBm at BT1 side. Write and read MOD_OPER_LW register with value 0x0000 to enable the clock start stop timing only for Frequency offset estimation module.(clock will be on from RSSI detection to Access address match). Write and read MOD_OPER_LW register with value 0x0020 to disable the clock start stop timing for Frequency offset estimation module. (clock will be on for entire RX)

Case 1: FreqOffClkCtrl disabled Contd.. Expected outcome: Time = 537.101us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b1, wModCntrlFreqOffEstClkG:1’b1 Time =1115.85 us -> wRegBankFreqOffClkCtrl:1’b0, rFreqOffEstClkEnb: 1’b0, wModCntrlFreqOffEstClkG:1’b0 Case 2: FreqOffClkCtrl enabled Expected outcome: Time = 419.97us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, wModCntrlFreqOffEstClkG:1’b1 Time =1115.85 us -> wRegBankFreqOffClkCtrl:1’b1, rFreqOffEstClkEnb: 1’b1, wModCntrlFreqOffEstClkG:1’b1 Understanding: Clock will be selected based on the configured bit.

Register name: FRQ_DRFT_THSLD_LW - FREQ_DRIFT_THRESHOLD bit and FRQ_DRFT_THSLD_UW - FREQ_DRIFT_LIMIT_VALUE bit Register Address: 0x660, 0x662 Testcase ID: mod_reg_drft_max_limit.c Purpose: Test if the configured maximum threshold value and limit value qualifies the frequency drift estimation. Description: Set attenuation value = -85 dBm at BT1 side. Write and read FRQ_DRFT_THSLD_LW register with maximum drift threshold value 0x0064. Write and read FRQ_DRFT_THSLD_UW register with drift limit value 0x0000 to 0x0064. Understanding: Maximum drift threshold is the maximum drift allowed which is 100KHz.(Programmed in Channel Model) Limit value is applied whenever the drift estimation exceeds the programmed value (i.e the value in channel model). Case 1: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x64, Limit value = 0x64  All packets received Case 2: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x64  All packets received Case 3: Frequency Drift = 100KHz(Channel model), Maximum Drift Threshold = 0x00, Limit value = 0x30  Packet reception is degraded.