Interrupt

Busy waiting

SFRs for Interrupt IP: Interrupt Priority Register IE: Interrupt Enable Register SCON contains RI, TI TCON contains EX0, EX1, TF0, TF1

The 8051 has five interrupt sources. Two external interrupts are provided through pins INTO-bar and INT1-bar, which are the alternate functions of port 3 pin 2 and port 3 pin 3, respectively. Two internal interrupts are generated by timer 0 overflow and by timer 1 overflow. The serial port on the 8051 can generate an interrupt when a byte has been transmitted or when a byte is received. Interrupt Flag Location External 0 IE0 TCON.1 External 1 IE1 TCON.3 Timer 0 TF0 TCON.5 Timer 1 TF1 TCON.7 Serial Port Receive RI SCON.0 Serial Port Transmit TI SCON.1

When an interrupt occurs the following happens: The current instruction completes execution. The PC is saved on the stack (ie; the address of the next instruction). The address of the ISR for the interrupt is loaded into the PC. Interrupt ISR

Interrupt Vector When an interrupt occurs the address of the interrupt service routine is loaded into the PC. This address is known as the interrupt vector. Interrupt Flag Vector System reset RST 0000H External interrupt 0 IE0 0003H Timer 0 TF0 000BH External interrupt 1 IE1 0013H Timer 1 TF1 001BH Serial port RI or TI 0023H

ISR Locations There are only eight memory locations between the vectors. Interrupt ISR Location ISR Length (bytes) System reset 0000H0002H 3 External interrupt 0 0003H000AH 8 Timer 0 000BH0012H External interrupt 1 0013H001AH Timer 1 001BH0022H Serial port 0023H002AH

Enabling and Disabling Interrupts On power-up or reset all interrupts are disabled. To enable interrupts we set the appropriate bits in the interrupt enable (IE) SFR. To disable an interrupt we simply clear the appropriate interrupt enable bit. IE register Symbol Bit Number Description EA 7 Enable/disable all interrupts. If this bit is cleared all interrupts are disabled. If it is set each interrupt source is individually enabled or disabled by setting or clearing the appropriate enable bit, as detailed below. -- 6   5 ES 4 Enable/disable serial port interrupts (set to enable, clear to disable). ET1 3 Enable/disable timer 1 overflow interrupt (set to enable, clear to disable). EX1 2 Enable/disable external 1 interrupt (set to enable, clear to disable). ET0 1 Enable/disable timer 0 overflow interrupt (set to enable, clear to disable). EX0 Enable/disable external 0 interrupt (set to enable, clear to disable). To enable the timer 0 overflow interrupt SETB EA SETB ET0 To disable the timer 0 overflow interrupt CLR ET0 For example

An ISR CAN be interrupted by an interrupt of higher priority. The 8051 has only two interrupt priority levels, 0 and 1, with 1 being the high priority. An ISR CAN be interrupted by an interrupt of higher priority. An ISR cannot be interrupted by an interrupt of the same or lower priority. The interrupt priority (IP) SFR: Symbol Bit Number Description -- 7   6 5 PS 4 Serial port interrupt priority level. PT1 3 Timer 1 interrupt priority level. PX1 2 External interrupt 1 priority level. PT0 1 Timer 0 interrupt priority level. PX0 External interrupt 0 priority level.

Polling sequence When more than one interrupts occur at the same time External 0  Timer 0 Overflow External 1 Timer 1 Overflow Serial Port.