Introduction to Micro Controllers & Embedded System Design Timer Operation Department of Electrical & Computer Engineering Missouri University of Science & Technology hurson@mst.edu A.R. Hurson

We begin with a general view of timers as they are common in microprocessor/microcontroller. Then we will focus on 8051 on-chip timers. A.R. Hurson

A timer is a series of divide-by-two flip flops that receive an input signal as a clock source. The clock is applied to the first flip flop which divides the clock frequency by two. The output of the first flip flop clocks the second one, which also divides the input by two, and so on. A.R. Hurson

LSB MSB Clock Q0 Q1 Q2 Flag Q0 D Clock Q1 Q2 Q + 5V   Clock Q1 Q2 Q LSB MSB + 5V Clock Q0 Q1 Q2 Flag Flag is set on 7-to-0 timer overflow A.R. Hurson

So a timer with n stages divides the input clock frequency by 2n. It is clear that the 1st stage (Q0) toggles at ½ the clock frequency, the 2nd stage at ¼ the clock frequency, and so on. So a timer with n stages divides the input clock frequency by 2n. The output of the last stage clocks a timer overflow flip flop, or flag, which is tested by software or generates an interrupt. A.R. Hurson

The binary value in the timer flip flops can be thought of as a “counter” of the number of clock pulses since the timer was started. A 16-bit timer would count from 0000H to FFFFH. The overflow flag is set on the FFFFH-to-0000H of the count. A.R. Hurson

In 8051, there are 2 16-bit timers with four modes of operations. A third 16-bit timer with three modes of operations is added in 8052. Timers are used for: Internal timing, Event counting, or Baud rate generation for the built-in serial port. A.R. Hurson

In internal timing applications, a timer is programmed to overflow at a regular interval and set the timing overflow flag. The flag is then used to synchronize the program to perform an action such as checking the state of inputs or setting data to outputs. Other applications can use the regular clocking of timer to measure the elapse time between two conditions. A.R. Hurson

Event counting is used to determine the number of occurrences of an event rather than to measure the elapse time between events. An event is any external stimulus that provide a 1-to-0 transition on a pin on the 8051 IC. The timer can also provide the baud rate clock for 8051’s internal serial port. A.R. Hurson

The 8051 timers are accessed using six special function registers: Timer SFR Purpose Address Bit addressable TCON Control 88H Yes TMOD Mode 89H No TL0 Timer 0 low-byte 8AH TL1 Timer 1 low-byte 8BH TH0 Timer 0 high-byte 8CH TH1 Timer 1 high-byte 8DH A.R. Hurson

Byte address Byte address 90 8D 8C 8B 8A 89 88 87 83 82 81 80 P1 TH1 TL1 TL0 TMOD TCON PCON DPH DDL SP P0 FF F0 E0 D0 B8 B0 A8 A0 99 98 Byte address B ACC PSW IP P3 IE P2 SBUF SCON A.R. Hurson

Timer MODe register: It contains two groups of four bits that set the operation mode for Timer 0 and Timer 1. Bit Name Timer Semantic 7 Gate 1 6 Counter/timer select bit: 1 = event counter 0 = interval timer 5 M1 Mode bit 1 4 M0 Mode bit 0 3 Timer 0 gate bit 2 Timer0 Counter/timer select bit Timer 0 mode bit 1 Timer 0 mode bit 0 A.R. Hurson

Timer MODe register: Timer modes M1 M0 Mode Semantic 13-bit timer mode (8048 model) 1 16-bit timer mode 2 8-bit auto-reload mode 3 Split timer mode: Timer 0: TL0 is an 8-bit timer controlled by timer 0 mode bits; TH0, the same except controlled by timer 1 mode bits Timer 1: stopped A.R. Hurson

Timer CONtrol register: It contains the status and control bits for timer 0 and timer 1. The upper four bits in TCON (i.e., TCON.4- TCON.7) are used to turn the timers on and off (TR0, TR1), or to signal a timer overflow (TF0,TF1). The lower 4 bits (i.e., TCON.0-TCON.3) have nothing to do with the timers. They are used to detect and initiate external interrupts. A.R. Hurson

Timer CONtrol register: Bit Symbol Address Semantic TCON.7 TF1 8FH Timer1 overflow flag. Set by hardware upon overflow; cleared by software or hardware when processor vectors to interrupt service routine TCON.6 TR1 8EH Timer1 run-control bit. Set/cleared by software to turn timer on/off TCON.5 TF0 8DH Timer0 overflow flag TCON.4 8CH Timer0 run-control bit A.R. Hurson

Timer CONtrol register: Bit Symbol Address Semantic TCON.3 IE1 8BH TCON.2 IT1 8AH External interrupt1 type flag. Set/cleared by software TCON.1 IE0 89H External interrupt0 flag. TCON.0 IT0 88H External interrupt0 type flag A.R. Hurson

Timer Modes and overflow flag 13-bit Timer mode (Mode 0): This is a 13-bit timer mode that provides compatibility with 8051 predecessor (i.e., 8048). The upper three bits of TLx are not used. Timer clock TLx (5 bits) THx (8 bits) Overflow flag TFx A.R. Hurson

Timer Modes and overflow flag 16-bit Timer mode (Mode 1): This is a 16-bit timer mode and similar to mode0. As the clock pulses are received, the timer counts up: i. e., 0000H,0001H, 0002H, …. An overflow occurs on the transition from FFFFH-0000H counts that sets the timer overflow flag. The timer continues to count. The overflow flag is the TFx bit in TCON that is read or written by software. A.R. Hurson

Timer Modes and overflow flag: Mode 1 The MSB of the value in the timer register is THx bit 7 and LSB is TLx bit 0. The LSB toggles at the input clock frequency divided by 2 and the MSB toggles at the input clock frequency divided by 216 = 65,536. The timer registers (TLx/THx) may be read or written at any time by the software. Timer clock TLx (8 bits) THx (8 bits) Overflow flag TFx A.R. Hurson

Timer Modes and overflow flag 8-bit Auto-reload mode (Mode 2): In this mode, the timer low- byte (TLx) operates as an 8-bit timer while the timer high-byte (THx) holds a reload value. When the counts overflows from FFH, not only the timer flag is set, but also the value in THx is loaded into TLx. If THx contains 4FH, the timer counts continuously from 4FH to FFH. A.R. Hurson

Timer Modes and overflow flag: Mode2 Timer clock TLx (8 bits) Overflow flag THx (8 bits) TFx Reload A.R. Hurson

Timer Modes and overflow flag Split timer mode (Mode 3): This mode is different for each timer: Timer 0 in mode 3 is split into two 8-bit timers. TL0 and TH0 acting as separate timers with overflows setting TF0 and TF1, respectively. Timer 1 stopped in mode 3, but can be started by switching it into one of the other modes. A.R. Hurson

Timer Modes and overflow flag: Mode 3 Mode 3 essentially provides an extra 8-bit timer: The 8o51 appears to have a third timer. When timer 0 is in mode 3, Timer 1 can be turned on and off by switching it out of and into its own mode 3. It can be used by the serial port as a baud rate generator, or it can be used in any way not requiring interrupts (since it is no longer connected to TF1). A.R. Hurson

Timer Modes and overflow flag: Mode 3 Timer clock TLx (8 bits) THx (8 bits) Timer clock TL0 (8 bits) Overflow flag TF0 Fosc/12 TH0 (8 bits) Overflow flag TF1 A.R. Hurson

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Bit number Function Pin Number Remarks P3.0 RxD 10 Serial communication P3.1 TxD 11 P3.2 12 External Interrupt P3.3 13 External interrupt P3.4 T0 14 Timer 0 P3.5 T1 15 Timer 1 P3.6 16 External Memory P3.7 17 A.R. Hurson

Clocking Sources  12 Oscillator  T0 orT1 0 = interval Timing   T0 orT1 0 = interval Timing 1 = Event Counting A.R. Hurson

Starting/Stopping and Controlling the Timers The simplest way to staring and stopping the timers is with the run control bit (i.e., TRx) in TCON register. TRx is cleared after a system reset, therefore the timers are disabled (stopped) by default. TRx is set by the program to start the timers. A.R. Hurson

Starting/Stopping and Controlling the Timers SETB TR0 ; Starts Timer 0 CLR TR0 ; Stops Timer 0    0 = Timer stopped 1 = Timer started Timer Clock A.R. Hurson

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 Starting/Stopping and Controlling the Timers ) Use the following diagram, tabulate the bit and byte addresses for timer registers and control bits.   Oscillator  12  T1 (P3.5) TL1 TH1 TF1 TR1 GATE   ) A.R. Hurson

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Initializing and Accessing Timer Registers Timers are usually initialized once at the beginning of a program to set the correct operating mode. During the course of the program, the timers are started, stopped, flag bits tested, cleared, and so on, as required by the application. A.R. Hurson

Initializing and Accessing Timer Registers TMOD is the first register to be initialized, since it sets the mode of operation. Of course Timer 1 is not activated until its run control bit (TR1) is set. If an initial count is necessary, the timer register TL1/TH1 must also be initialized. Note: The counters count up and set the carry flag on an FFFFH-to- 0000H transition.   A.R. Hurson

MOV TL1, #9CH ; These two instructions initializes MOV TH1, #0FFH ; the timer by _100H SETB TR1 ; Starts the timer and as the result ; the overflow flag (TF1) is set 100 ; sec later. During this time the ; program remain in a “wait loop” WAIT: JNB TF1, WAIT ; when the timer overflows, we need ; to stop the timer and clear the ; overflow flag CLR TR1 CLR TF1 A.R. Hurson

Example: Write a program that creates a periodic waveform on P1.0 Duration of this loop is 4 machine cycle. A 12 MHz crystal results in a 1 sec clock. So the duration of this loop is 4 sec. Adding NOPs in the loop allows us to extend this. ORG 8100 8100 D290 LOOP: SETB P1.0 ; one machine cycle C290 CLR P1.0 ; one machine cycle 80FA SJMP LOOP ; two machine cycle END A.R. Hurson

Short intervals and Long intervals A 12 MHz crystal results in an on-chip clock of 1 MHz. The short interval is limited by the software not the timer clock and this is the duration of instructions. The shortest instruction in 8051 requires one machine cycle or 1 micro second. A.R. Hurson

Maximum interval (sec) Short intervals and Long intervals The following table summarizes the techniques for creating intervals of various length. Maximum interval (sec) Technique  10 software 256 8-bit timer with auto-reload 65536 16-bit timer No limit 16-bit timer plus software loops A.R. Hurson

Example: Write a program using Timer 0 to create a 10KHz square wave on P1.0 ORG 8100 8100 758902 MOV TMOD, #02H ; 8-bit auto-reload mode 8103 758CCE MOV TH0, #-50 ; reload value to TH0 8106 D28C SETB TR0 ; Start timer 8108 308DFD LOOP: JNB TF0, LOOP ; Wait for overflow 810B C28D CLR TF0 810D B290 CPL P1.0 810F 80F7 SJMP LOOP END A.R. Hurson