EUDET – LPC- Clermont VFE Electronics

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Presentation transcript:

EUDET – JRA3 @ LPC- Clermont ----- VFE Electronics G.Bohner – R.Cornat - P.Gay - J.Lecoq - S.Manen - L.Royer with R.Bonnefoy and M.Crouau contribution

Ecal VFE Electronics ADC M U X LAL LAL/LPC LPC A N low gain L O G one ADC for x channels 10 bits amp. shaper high gain medium gain low gain comp. M U X A N L O G E R Y ADC LAL est-ce que la conso tient compte du power pulsing ou non ??

Developments @LPCC Wilkinson ADC Pipeline ADC Cyclic ADC included in SKIROC chip (11/06) Pipeline ADC 10 bits version “fully” tested Cyclic ADC in development Switched integrator and analog memory est-ce que la conso tient compte du power pulsing ou non ??

Wilkinson ADC Characteristics: Technology: Austriamyc. BiCMOS SiGe 0.35µm Power supply: 3.5V (digital: 2.5V) Clock frequency: 50 MHz Differential architecture Gray counter est-ce que la conso tient compte du power pulsing ou non ??

Performance (simulated): Wilkinson ADC Performance (simulated): Resolution: 12 bits Consumption: 3 mW Conversion time: 80 µs (@ 50MHz) Integrated cons.: (3mW * 80µs)/200ms= 1.2µW Current source (ramp generator): Temperature sensitivity : 40 ppm/°C max (20 to 50°C) Power supply sensitivity: 5 ppm/°C (±50 mV) Input dynamic signal: 1V Common Mode 2V differential ramp generator est-ce que la conso tient compte du power pulsing ou non ??

Performance (simulated): Wilkinson ADC Performance (simulated): Linearity: ramp generator < ± 250 µV est-ce que la conso tient compte du power pulsing ou non ??

Performance (simulated): Wilkinson ADC Performance (simulated): Linearity: global chip < ± 500 µV up to 125mV < 0.1% from 125mV to 1V Linearity error (mV) est-ce que la conso tient compte du power pulsing ou non ?? 0.125V 1V

Wilkinson ADC Conclusion: suitable for SKIROC requirements SLOW ADC: sampling rate  10kHz LOW Integ. consumption: 1.2 µW GOOD resolution: 12 bits GOOD integration: die surface = 0.12mm2 LOW sensitivity to T° & Power Supply variations suitable for SKIROC requirements Layout geometry adapted for SKIROC Power pulsing included To be tested at Clermont with the SKIROC test board (LAL) est-ce que la conso tient compte du power pulsing ou non ??

Pipeline ADC Characteristics: Technology: Austriamyc. CMOS 0.35µm Power supply: 5V 10 stages; 1.4mm2 Clock frequency: 4 MHz Differential architecture 1.5 bit per stage archit.  to relax offset constraints on comparators est-ce que la conso tient compte du power pulsing ou non ??

Pipeline ADC Test Bench: Generic for ADC tests board Dedicated mezzanine board Analog signal generator: DAC 16 bits (DAC8830) Reference : ADC 16bits (AD7684) PC/LabView Slow Control through USB interface Data process with Scilab program Chip under test USB link est-ce que la conso tient compte du power pulsing ou non ??

Performance (measured): Pipeline ADC Performance (measured): Resolution: 10 bits Consumption: 35 mW Integrated cons.: (35mW * 0.25µs)/200ms= 0.044µW Sampling rate: 4 MHz Input dynamic: 2V est-ce que la conso tient compte du power pulsing ou non ??

Pipeline ADC Linearity (measured): Input signal: ramp from 0 to 2V 2048 steps -- 50 measurements / step Integral Non Linearity (INL): +0.85/-0.70 LSB Differential Non-Linearity (DNL): -0.56/-0.46 LSB Noise (1): 0.47 LSB est-ce que la conso tient compte du power pulsing ou non ??

Pipeline ADC Conclusion: A 10-bits 4-MS/s 35-mW pipeline ADC validated A 3V version under test (one sihgle stage)  20 mW (≠ 35mW/5V) Publication in progress est-ce que la conso tient compte du power pulsing ou non ??

Cyclic ADC: in development Compare to a pipeline ADC with m stages: Sampling rate divided by m Consumption divided by m Same integrated consumption Die area divided by m A unique stage  can be optimized (capacitors matching, calibration) 1 ADC/channel Performance expected: 12 bits precision < 20 mW Sampling rate:  1MHz Integ. cons.: < 0.1µW est-ce que la conso tient compte du power pulsing ou non ??

ADCs: summary status Best final candidate: cyclic ADC # bits Precision Integ. consum. Die area Status Wilkinson 12 12 bits @ low energy 10 bits @ high energy 1.2 µW 0.12mm2 in SKIROC Pipeline 10 10 bits 0.04 µW 1.4mm2 tested Cyclic 12 bits < 0.1µW  0.15 mm2 in developt Best final candidate: cyclic ADC est-ce que la conso tient compte du power pulsing ou non ??

Short term plans Tests of Wilkinson ADC in SKIROC1  to be started end of April 07 at Clermont/Orsay Tests of the 3V single stage pipeline ADC  in progress Cyclic ADC prototype design  AMS run in June 07  Tests in Sept./Oct. 07 Cyclic ADC included in new SKIROC2 (2 versions)  AMS run in November 07 SKIROC3 EUDET production with the validated ADC  March 2008 est-ce que la conso tient compte du power pulsing ou non ??

Schedule April May June July Aug. Sept. Oct. Nov. Dec. SKIROC test (Wilkinson ADC) 3V 1-stage ADC test Cyclic ADC design Cyclic ADC test ADC included in SKIROC est-ce que la conso tient compte du power pulsing ou non ??