Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard VFE & PCB Status & schedule of production Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard Presented by Julien Fleury

Plan Measurement result on FLC_PHY1 - Linearity & dynamic range - Pedestal dispersion & noise Introducing the new FLC_PHY2 front end chip General presentation The new charge preamplifier The new shaper The new track & hold Schedule of the front-end electronic group Front-end chip & PCB schedule

Meas. Results – linearity & dyn. range Linearity measured : Preamplifier linearity .…………………………. 0.1% Direct shaper output linearity………………. 0.3% Multiplexed output ………………………………. 0.2% Simulation Measurement Dynamic range : Measured .…………………………. 3.5 pC (550 MIP) Simulated…………………………… 4.2 pC (650 MIP)

Meas. Results – Pedestal disp & noise Noise measured : Cline .…………………………………….. 80pF Peaking time………………………… 200 ns Measured noise …………………… 2200e- Pedestal dispersion Pedestal dispersion measured : Average .……………………………… -3.129V Standard deviation………………. 5mV Excursion ……………………………. 17mV Settling time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Meas. Results – Conclusion FLC_PHY1 reachs expectation for physics prototype Vbiasm_pa Out 0 Out 1 Out 2 Out 3 Out 4 Out 6 Out 5 Out 8 Out 10 Out 9 Out 7 Out 12 Out 13 Out 15 Out 14 Out 11 Vdda In 0 Vbiasi_pa Vb_casc V_rf Vf Vbiaso_pa Vbiasi_sh Vbiaso_sh H R Vss Vbias_cell In 16 Ck_R In 1 In 2 In 3 In 4 In 5 In 6 In 7 In 8 In 9 In 10 In 11 In 12 In 15 In 14 In 13 SW1 In 17 Vdd SW2 Out_pa Q_R Bias_buf Out Bias_out Out17 Out 16 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 24 22 23 31 30 29 28 27 26 25 40 39 38 32 37 36 35 34 33 47 46 45 44 43 42 41 51 50 49 48 56 57 58 59 60 61 62 63 64 55 54 53 52 FLC_PHY1 CQFP 64 package Rst_R Noise Linearity Dyn.range

New FLC_PHY2 – General presentation Pin-Pin compatibility FLC_PHY2 Preamp  1 gain (1.5pF) Low noise (2200e-) Shaper  Mono gain unipolar track & hold  Unipolar Preamp  16 gains (0.2, 0.4, 0.8, 1.6pF switchable) Lower noise (input trans improved) Shaper  bigain differential track & hold  differential Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel

New FLC_PHY2 – charge preamp Characteristics 4 switchable feedback capa Max out from 801300 MIP input PMOS size increased noise reduced Hardware configuration No modification of the read-out interface Gain switches driven on VFE board 50 1 0.2pF 0.4pF 0.8pF 1.6pF 1pF 2pF 4pF

New FLC_PHY2 – shaper Old version New version + - Filter structure stays (CRRC) High gain amplifier is replaced by an OP AMP Differential structure makes the pedestal dispertion lower The OP AMP have been designed and layouted in LAL (used in OPERA slow shaper) Old version New version C1 R1 C2 R2 C1 R1 C2 R2 - +

New FLC_PHY2 – shaper Peaking time is 200ns on both gain High-gain shapers can be shut down by switching off their biases Two different output for low gain and high gain Interface compatibility with the read out is kept New interface not written at this point Transcient simulation Linearity simulation

New FLC_PHY2 – track & hold Including a Widlar structure (differential) to reduce pedestal dispersion Common collector buffer structure is kept for safety Memory capacitance is increased from 1 to 2pF

New FLC_PHY2 – Conclusion Pin to pin compatibility with FLC_PHY1  to simplify PCB design Read out interface compatibility with FLC_PHY1  R&D on the front end chip has no influence on PCB and RO development Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel

Schedule – Front end chip & PCB Design Fab Test Production FLC_PHY1 Test Standby Choice Production FLC_PHY2 Design Foundry Test April, 7th June, 23rd Sept. November GOAL : Be ready for cosmics test in february 2004  Build VFE boards in January 2004