Day 26: November 11, 2011 Memory Overview ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: November 11, 2011 Memory Overview Penn ESE370 Fall2011 -- DeHon

Today Memory Project 2 is on this (posted) Motivation Organization Basic components Optimization concerns Project 2 is on this (posted) Not looked at midterms  try for Monday Penn ESE370 Fall2011 -- DeHon

Know how to store state Penn ESE370 Fall2011 -- DeHon

Register Storage Could just put together a large number of registers Concerns? Penn ESE370 Fall2011 -- DeHon

Concerns? Large number of wires May want to store for many cycles Could determine area 5l wire pitch  how wide? May want to store for many cycles Penn ESE370 Fall2011 -- DeHon

Usage Scenario How many state values read on each cycle? Penn ESE370 Fall2011 -- DeHon

Concerns? Large number of wires May want to store for many cycles Could determine area May want to store for many cycles Not able to update all on every cycle Not able to use all on every cycle Penn ESE370 Fall2011 -- DeHon

Limited Data Use What else do we need to share the wires if can only use one register on each cycle? Use with shared data path Need to select the one output Can only update one Need to control which one gets written Penn ESE370 Fall2011 -- DeHon

Limited Data Use Add load enable to register Logic to enable one register on write Mux to select output Penn ESE370 Fall2011 -- DeHon

Good Solution? Could get away with just latch Not full register with master/slave latch Pay large amount for decode and mux Proportional to memory bits Penn ESE370 Fall2011 -- DeHon

Memory Idea Maximize storage density (bits/cm2) By minimizing the size/complexity of the repeated element Use shared periphery circuits to provide full functionality Trades off bandwidth (concurrent access) to save area Penn ESE370 Fall2011 -- DeHon

Memory Bank Penn ESE370 Fall2011 -- DeHon

Share Address Decode Word – group of bits read/written together All have same control Penn ESE370 Fall2011 -- DeHon

Share Address Decode Words Mux select bits (words) from row read When only want a subset Penn ESE370 Fall2011 -- DeHon

Share Address Decode Result: only spend N0.5 area (perimeter) on selecting rather than linear in bits Penn ESE370 Fall2011 -- DeHon

Gate Density When is 14n > 6n+32*sqrt(n) ? Penn ESE370 Fall2011 -- DeHon

Memory Row Use shared enable for wire economy Word line Penn ESE370 Fall2011 -- DeHon

Memory Column Use shared bus for area and wire economy Row enable selects the cells to read/write from bus Penn ESE370 Fall2011 -- DeHon

Memory Cell Hold data Conditionally drive onto output bus Conditionally overwritten with data from bus Penn ESE370 Fall2011 -- DeHon

SRAM Memory bit Penn ESE370 Fall2011 -- DeHon

SRAM Memory bit Core is back-to-back inverters for storage Like static latch Penn ESE370 Fall2011 -- DeHon

SRAM Memory bit Core is back-to-back inverters for storage Like static latch To minimize size, doesn’t include disable Penn ESE370 Fall2011 -- DeHon

SRAM Memory bit Pass gate mux for output to column Bit-Line (BL) Penn ESE370 Fall2011 -- DeHon

SRAM Memory bit How do we write into this cell? No directionality to pass gate If drive BL strong enough, can flip value in selected cell Ratioed operation Penn ESE370 Fall2011 -- DeHon

Column Capacitance What is capacitance of bit line (column)? Waccess (M5,M6) – transistor width of column device d rows g=Cdiff/Cgate Penn ESE370 Fall2011 -- DeHon

Time Driving Bit Line In terms of Waccess, Wbuf (M1,M3), d For Waccess=Wbuf=1, d=512, g=0.5 Penn ESE370 Fall2011 -- DeHon

Column Capacitance Consequence Want Waccess, Wbuf small to keep memory cell small Increasing Waccess, also increases Cbl Don’t really win by sizing up Driving bit line will be slow Penn ESE370 Fall2011 -- DeHon

Column Sensing Speedup read time by sensing limited swing Sense circuit detects small change in bit line voltage(s) Precharge to intermediate voltage BL and /BL swing opposite directions Amplifies for output Penn ESE370 Fall2011 -- DeHon

Output Amps Bottom of array includes Sense Amplifiers from bit lines to output Penn ESE370 Fall2011 -- DeHon

Column Write Writes driven from outside array Use large driver Strong enough to flip memory bit Strong so can charge column quickly Disable when not write Be careful on your project2 Could overwrite wrong row Penn ESE370 Fall2011 -- DeHon

Complete Memory Bank Penn ESE370 Fall2011 -- DeHon

Admin Project 2 out Andre away on Tuesday Due November 23 Note recommend milestones Andre away on Tuesday No office hour Tuesday Will be back for Wednesday lecture Penn ESE370 Fall2011 -- DeHon

Idea Memory for compact state storage Share circuitry across many bits Minimize area per bit  maximize density Aggressively use: Pass transistors, Ratioing Precharge, Amplifiers to keep area down Penn ESE370 Fall2011 -- DeHon