Robert Brayton Alan Mishchenko Department of EECS UC Berkeley Task ID: 2710.001 SAT-based Methods for Scalable Synthesis and Verification Robert Brayton Alan Mishchenko Department of EECS UC Berkeley

Task Overview SRC task ID: 2710.001 Start date: 1-Nov-2016 Thrust area: CADT Task leaders: Robert K. Brayton, Univ. of California/Berkeley Alan Mishchenko, Univ. of California/Berkeley Industrial liaisons: See next slide Students: Yen-Sheng Ho (Mentor intern, graduating 2017)

Industrial Liaisons IBM Intel Mentor Graphics Jason Baumgartner Victor Kravets Intel Timothy Kam Steven Burns Michael Kishinevsky Mentor Graphics Jeremy Levitt

Anticipated Results Methodology and algorithms for next-generation improvements in logic synthesis, addressing reverse engineering SAT-based circuit restructuring precomputation of properties for practical Boolean functions Public software implementation of the above methodology and algorithms Experimental evaluation on industrial benchmarks.

Responding to the Needs of SRC Companies Reverse engineering enables applying word-level methods to gate-level problems. S3 System Tools S3.4 Advanced logic/physical/high-level synthesis and cross-boundary optimization Scalable synthesis leads to scalable verification V1 Verification Core Technologies V1.1 Advances in the scalability of automated model checking and sequential equivalence checking techniques for bit-level and bit-vector models V1.2 Advances in techniques: general-purpose SAT solvers; constraint solving techniques; SAT solvers tuned for specific applications; automatic abstraction and abstraction-refinement; satisfiability modulo theories (SMT) V1.3 Novel and improved algorithms for optimizing design and specification logic. Computing complete test-suites for multiple-fault testing using different fault models T1 Test Cost and Quality Improvement T1.1 Test cost reduction T1.4 Methods to improve test quality by effective test pattern selection across fault models SAT-based formulations can contribute to other areas S3.5 Fundamental/significant place/route improvements, including how to scale the methods for multi-core designs and reliability-aware place and route There has been continued interest from the SRC companies IBM, Mentor Graphics

Task Deliverables 31-Oct-2017 Software release of the RE engine and RE-enhanced equivalence checking engine. Evaluation on industrial problems. 31-Oct-2018 Software release of SAT-based logic restructuring. Evaluation on industrial problems. 31-Oct-2019 Software release of computation of Boolean properties with applications to network optimization. Evaluation on industrial problems. Final report summarizing research accomplishments and future direction. https://www.src.org/library/research-catalog/2710.001/

Background and Motivation Reverse engineering Discovering high-level structure in gate-level netlists Useful for both verification and synthesis SAT-based circuit restructuring Global, incremental, and exhaustive Useful for delay/area optimization before and after mapping The “genome project” of logic synthesis Precomputing useful functional properties of practical Boolean functions up to 16 inputs For example, exhaustive enumeration of non-redundant circuit structures for small practical functions will be used Useful for incremental resynthesis before and after mapping AIG rewriting is one special case

Summary of Recent Progress for Each Technical Goal 1st year: Reverse engineering Presented last year 2nd year: SAT-based circuit restructuring Improved algebraic factoring based on hashing (ASP-DAC’17) Improved SAT-based area recovery after mapping (ASP-DAC’18) SAT-based canonical computations with applications in logic synthesis and formal verification (DAC’18) Winning 2017 HWMCC largely by improving SAT-based methods Winning 2017 ICCAD CAD competition Problem A (Synthesizing target functions in ECO using SAT-based methods) (DAC’18) Winning 2016 ICCAD CAD competition Problem A (Equivalent fault computation using SAT-based methods) (TCAD’18) 3rd year: The “genome project” of logic synthesis Initial work on QBF-based enumeration of delay-optimizing circuit structures (DATE’17) and improved exact synthesis (DATE’18)

Comparison with Existing Work SAT-based canonical computations in logic synthesis - Extended LEXSAT (introduced by Knuth) and introduced a novel SAT-based algorithm, LEXUNSAT, which computes a canonical abstraction of the UNSAT core - Applied them to ISOP computation and CEX minimization, getting better results SAT-based area recover after technology mapping - Improved quality, paving the way to a fully SAT-based technology mapper SAT-based computations in ICCAD CAD competitions 2016-2017 - Won the 2016 competition on computing equivalent faults using SAT - Won the 2017 competition to synthesizing patch functions in ECO using SAT Novel integration of simulation and SAT - Substantially improved several applications based on simulation and SAT - Better runtime and scalability in several ABC commands (dch, fraig, dress, scorr, pdr)

Research Overview The following slides present three most important research results since the last review SAT-based canonical computations A novel integration of simulation and SAT solving Award-winning SAT-based ECO

Result 1: Canonical SAT In SAT-based computations, we can get canonical results! This is achieved without building a canonical representation or modifying the CNF generator and the SAT solver Canonical means that there is a unique result for any Original circuit structure CNF derived from this circuit SAT solver used to solve this CNF Canonical results include major artifacts returned by the SAT solver Counter-examples Abstractions of UNSAT cores These results take longer to compute but (in addition to being canonical) they have a higher quality, for example: An implicant computed for the function is prime A support computed for the node is minimal

Pseudo-code of LEXUNSAT Input: cnf F Output: the smallest satisfying assignment as literals in array A array LEXUNSAT( cnf F ) { Initialize array A to have all positive literals in the given order; for ( i = 0; i <|A|; i++ ) { if ( F is UNSAT under assumptions in A without A[i] ) invert the polarity of literal A[i] to be negative; } return A; A. Mishchenko, R. Brayton, A. Petkovska, M. Soeken, L. Amaru, and A. Domic, "Canonical computation without canonical representation", Accepted at DAC'18. https://people.eecs.berkeley.edu/~alanmi/publications/2018/dac18_canon.pdf

Result 2: More Effective Integration of Simulation and SAT Simulation and SAT have been used together for a long time Simulator disproves many properties, which saves SAT solver’s runtime SAT solver proves the correct properties and disproves those properties that are hard to disprove, thereby helping simulator Our contributions are a better understanding of how simulation and SAT should be orchestrated, leading to a new And-Inverter Graph (AIG) package that includes additional bookkeeping to make simulation and SAT faster and more scalable As a result, some of the key applications (such as computing node equivalences, structural choices, using don’t-cares, and others) become substantially (2x-5x) faster without reducing quality of results A. Mishchenko and R. Brayton, "Integrating AIG package, simulator, and SAT solver", Submitted to IWLS'18. https://people.eecs.berkeley.edu/~alanmi/publications/2018/iwls18_simsat.pdf

Novel Simulation / SAT Ecosystem

Result 3: SAT-Based ECO Engineering change order (ECO) is a problem of minimally patching a circuit to realize the Boolean function specified by another circuit A new SAT-based engine is implemented to derive the patch while minimizing its cost The engine was used in the 2017 ICCAD CAD competition and won the first place Part of the success of the proposed ECO, is because it is based on the canonical SAT-based procedure LEXUNSAT (this guaranteed minimality of the cost)

Illustration of SAT-Based ECO F(n, x)  S(x) … Outputs Implementation F(n, x) Specification S(x) n Node Inputs x Boolean space Resubstitution / ECO of n in terms of x exists iff I(x) x n F(n, x) == S(x) is true, that is x n F(n, x)  S(x) is false, that is F(0, x)  S(x) F(1, x)  S(x) x F(0, x)  S(x) & F(1, x)  S(x) is UNSAT Joint work with Ai Quoc Dao, Mark Po-Hung Lin, Jie-Hong Roland Jiang

Relevant Recent Publications SAT-based canonical computations in logic synthesis - A. Petkovska, A. Mishchenko, M. Soeken, G. De Micheli, R. Brayton, and P. Ienne, "Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications", Proc. ICCAD’16. - A. Mishchenko, R. Brayton, A. Petkovska, M. Soeken, L. Amaru, and A. Domic, "Canonical computation without canonical representation", Proc. DAC'18. SAT-based area recover after technology mapping - B. Schmitt, A. Mishchenko, and R. Brayton, “SAT-based area recovery in structural technology mapping”, Proc. ASP-DAC’18. SAT-based computations in ICCAD CAD competitions 2016-2017 - D. A. Quoc, M. P.-H. Lin, and A. Mishchenko, "SAT-based fault equivalence checking in functional safety verification", To appear in TCAD. - D. A. Quoc, M. P.-H. Lin, N.-Z. Lee, L.-C. Chen, J.-H. R. Jiang, A. Mishchenko, and R. Brayton, "Efficient computation of ECO patch functions", Proc. DAC’18. Novel integration of simulation and SAT - A. Mishchenko and R. Brayton, "Integrating AIG package, simulator, and SAT solver", Submitted to IWLS'18. Improved scalability in logic synthesis - B. Schmitt, A. Mishchenko, V. Kravets, R. Brayton, and A. Reis, "Fast-extract with cube hashing", Proc. ASP-DAC'17. - L. Amaru´, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, J. Olson, R. Brayton, and G. De Micheli, "Improvements to Boolean resynthesis", Proc. DATE’18. - V. N. Possani, Y.-S. Lu, A. Mishchenko, K. Pingali, R. P. Ribas, and A. I. Reis, "Parallel AIG rewriting", Submitted to IWLS’18.

Conclusions Reviewed the SRC task (second year) “SAT-based Methods for Scalable Synthesis and Verification” Discussed ongoing and forthcoming work Reviewed recent publications