An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

Slides:



Advertisements
Similar presentations
Doc.: IEEE /0071r1 Submission January 2004 Aleksandar Purkovic, Nortel NetworksSlide 1 LDPC vs. Convolutional Codes for n Applications:
Advertisements

Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.
Houshmand Shirani-mehr 1,2, Tinoosh Mohsenin 3, Bevan Baas 1 1 VCL Computation Lab, ECE Department, UC Davis 2 Intel Corporation, Folsom, CA 3 University.
Improving BER Performance of LDPC Codes Based on Intermediate Decoding Results Esa Alghonaim, M. Adnan Landolsi, Aiman El-Maleh King Fahd University of.
Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Diagonal Parity Structure Chanho Yoon, Eunyoung Choi, Minho Cheong.
Cooperative Multiple Input Multiple Output Communication in Wireless Sensor Network: An Error Correcting Code approach using LDPC Code Goutham Kumar Kandukuri.
ISSPIT Ajman University of Science & Technology, UAE
Near Shannon Limit Performance of Low Density Parity Check Codes
Computer Architecture Project
Code and Decoder Design of LDPC Codes for Gbps Systems Jeremy Thorpe Presented to: Microsoft Research
Interconnect Efficient LDPC Code Design Aiman El-Maleh Basil Arkasosy Adnan Al-Andalusi King Fahd University of Petroleum & Minerals, Saudi Arabia Aiman.
1 ACS Unit for a Viterbi Decoder Garrick Ng, Audelio Serrato, Ichang Wu, Wen-Jiun Yong Advisor: Professor David Parent EE166, Spring 2005.
The Role of Specialization in LDPC Codes Jeremy Thorpe Pizza Meeting Talk 2/12/03.
Factor Graphs Young Ki Baik Computer Vision Lab. Seoul National University.
Low Density Parity Check (LDPC) Code Implementation Matthew Pregara & Zachary Saigh Advisors: Dr. In Soo Ahn & Dr. Yufeng Lu Dept. of Electrical and Computer.
Block-LDPC: A Practical LDPC Coding System Design Approach
Wireless Mobile Communication and Transmission Lab. Theory and Technology of Error Control Coding Chapter 7 Low Density Parity Check Codes.
Matrix Sparsification. Problem Statement Reduce the number of 1s in a matrix.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
Tinoosh Mohsenin and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis Split-Row: A Reduced Complexity, High Throughput.
CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.
Hardware Implementation of a Memetic Algorithm for VLSI Circuit Layout Stephen Coe MSc Engineering Candidate Advisors: Dr. Shawki Areibi Dr. Medhat Moussa.
Optimal digital circuit design Mohammad Sharifkhani.
CHANNEL ESTIMATION FOR MIMO- OFDM COMMUNICATION SYSTEM PRESENTER: OYERINDE, OLUTAYO OYEYEMI SUPERVISOR: PROFESSOR S. H. MNENEY AFFILIATION:SCHOOL OF ELECTRICAL,
Distributed computing using Projective Geometry: Decoding of Error correcting codes Nachiket Gajare, Hrishikesh Sharma and Prof. Sachin Patkar IIT Bombay.
RICE UNIVERSITY “Joint” architecture & algorithm designs for baseband signal processing Sridhar Rajagopal and Joseph R. Cavallaro Rice Center for Multimedia.
Design of a High-Throughput Low-Power IS95 Viterbi Decoder Xun Liu Marios C. Papaefthymiou Advanced Computer Architecture Laboratory Electrical Engineering.
Introduction of Low Density Parity Check Codes Mong-kai Ku.
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multiprocessor Systems Zhiyi Yu, Bevan M. Baas VLSI Computation Lab, ECE department,
ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis
Real-Time Turbo Decoder Nasir Ahmed Mani Vaya Elec 434 Rice University.
Part 1: Overview of Low Density Parity Check(LDPC) codes.
Low Density Parity Check codes
Multi-Split-Row Threshold Decoding Implementations for LDPC Codes
1 Design of LDPC codes Codes from finite geometries Random codes: Determine the connections of the bipartite Tanner graph by using a (pseudo)random algorithm.
Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding Karkooti, M.; Cavallaro, J.R.; Information Technology: Coding and Computing, 2004.
Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder Lei Yang, Hui Liu, C.-J Richard Shi Transactions.
Memory-efficient Turbo decoding architecture for LDPC codes
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California,
A Low-Area Interconnect Architecture for Chip Multiprocessors Zhiyi Yu and Bevan Baas VLSI Computation Lab ECE Department, UC Davis.
Tinoosh Mohsenin 2, Houshmand Shirani-mehr 1, Bevan Baas 1 1 University of California, Davis 2 University of Maryland Baltimore County Low Power LDPC Decoder.
1 Aggregated Circulant Matrix Based LDPC Codes Yuming Zhu and Chaitali Chakrabarti Department of Electrical Engineering Arizona State.
Waseda University Low-Density Parity-Check Code: is an error correcting code which achieves information rates very close to the Shanon limit. Message-Passing.
Submitted To: Submitted By: Seminar On 8086 Microprocessors.
1 Architecture of Datapath- oriented Coarse-grain Logic and Routing for FPGAs Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer.
Optimizing Interconnection Complexity for Realizing Fixed Permutation in Data and Signal Processing Algorithms Ren Chen, Viktor K. Prasanna Ming Hsieh.
Error Correction and LDPC decoding
ECE Department, University of California, Davis
Computing and Compressive Sensing in Wireless Sensor Networks
OptiSystem applications: BER analysis of BPSK with RS encoding
Length 1344 LDPC codes for 11ay
VLSI Architectures For Low-Density Parity-Check (LDPC) Decoders
Q. Wang [USTB], B. Rolfe [BCA]
A Scalable Architecture for LDPC Decoding
Rate 7/8 LDPC Code for 11ay Date: Authors:
Rate 7/8 (1344,1176) LDPC code Date: Authors:
Progress report of LDPC codes
LDPC for MIMO Systems July 8, 2004 Jianuxan Du,
Sridhar Rajagopal and Joseph R. Cavallaro Rice University
Sridhar Rajagopal and Joseph R. Cavallaro Rice University
High Throughput LDPC Decoders Using a Multiple Split-Row Method
Yiyu Shi*, Wei Yao*, Jinjun Xiong+ and Lei He*
On-line arithmetic for detection in digital communication receivers
Chris Jones Cenk Kose Tao Tian Rick Wesel
المشرف د.يــــاســـــــــر فـــــــؤاد By: ahmed badrealldeen
Low-Density Parity-Check Codes
Potential of Non-Uniform Constellations with Peak Power Constraint
DSP Architectures for Future Wireless Base-Stations
On-line arithmetic for detection in digital communication receivers
DSPs for Future Wireless Base-Stations
Presentation transcript:

An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes Tinoosh Mohsenin, Dean Truong and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis

Outline Introduction LDPC Decoding Goals and Key Features Split-Row Threshold Decoding Method Error Performance Results Split-Row Threshold Decoder Implementation and Results Conclusion

LDPC Decoding Message passing decoding LDPC decoding challenges High interconnect complexity for large number of processing nodes Large delay, area, and power dissipation caused by long and global wire

Outline Introduction to LDPC Decoding Goals and Key Features Split-Row Threshold Decoding Method Error Performance Results Split-Row Threshold Decoder Implementation and Results Conclusion

LDPC Decoder Design Goals and Features Key goals Very high throughput and high energy efficiency Area efficient (small circuit area) Well suited for long-length and large row weight LDPC codes Easy implementation with automatic CAD tools Good error performance Split-Row decoding key features Reduced interconnect complexity Reduced processor complexity T. Mohsenin and B. Baas, “Split-row: A reduced complexity, high throughput LDPC decoder architecture,” in ICCD, 2006 T. Mohsenin and B. Baas, “High-throughput LDPC decoders using a multiple Split- Row method,” in ICASSP, 2007

Standard vs. Split-Row Decoding standard decoding Split-Row decoding = H split - sp 1 C V 3 5 8 10 reduction of check processor area reduction of input wires to check processor

MinSum vs. MinSum Split-Row Sign Magnitude MinSum: MinSum Split-Row:

Outline Introduction to LDPC Decoding Goals and Key Features Split-Row Threshold Decoding Method Error Performance Results Split-Row Threshold Decoder Implementation and Results Conclusion

MinSum Split-Row Threshold Algorithm A signal (Threshold_en) is passed from each partition, which indicates whether a partition has a minimum less than a given threshold (T). Based on Threshold_en status, the check nodes take as their minimum of their own local Min or T. Optimum threshold value (T) is obtained by empirical simulations Threshold_en Sp1=1 Threshold_en Sp0=0 MinSum Split-Row Threshold:

Impact of Threshold Selection 15 decoding iterations SNR=4.2 dB Optimum T=0.2 Optimum T=0.2 (6,32) (2048,1723) LDPC Code Optimum threshold (T) is independent of SNR and decoding iteration

Outline Introduction to LDPC Decoding Goals and Key Features Split-Row Threshold Decoding Method Error Performance Results Split-Row Threshold Decoder Implementation and Results Conclusion

Error Performance for (16,4) (1536,1155) LDPC Code In the Plot: BPSK modulation AWGN channel Based on 80 error blocks Maximum 15 iterations SPA: Sum Product Algorithm MS: MinSum Normalized For MS Split-Row Threshold T=0.3 0.08dB 0.42 dB

Multi-Split-Row Threshold Decoding Divide parity check matrix to Spn (Spn>2) partitions Partitioning can be arbitrary so long as there are at least two variable nodes per partition Example: (6,32) (2048,1723) LDPC Code 32/Spn variable nodes

Error Performance for (2048,1723) 10GBASE-T Code MS Split-Row-2 Threshold is 0.07 dB away from MS MS Split-Row-16 Threshold is 0.22 dB away from MS and is 0.12 dB better than Split-Row-2 Original. Decoder Split-2 Split-4 Split-8 Split-16 Optimum T 0.2 0.23 0.24 0.22 dB 0.12 dB

Outline Introduction to LDPC Decoding Goals and Key Features Split-Row Threshold Decoding Method Error Performance Results Split-Row Threshold Decoder Implementation and Results Conclusion

Comparison of Decoders (6,32) (2048,1723) 10GBASE-T code with 15 decoding iterations. 10GBASE-T Code 65 nm, 7 M, 1.3 V MinSum standard Split-2 Threshold Split-4 Threshold Split-8 Threshold Split-16 Threshold Split-16 vs.MinSum Area Utilization 25% 40% 85% 95% 98% 3.9x Area (mm2) 18.2 8.9 5.0 4.5 3.8 4.8x Speed (MHz) 17 40 53 112 101 5.9x Throughput @ 15 iter (Gbps) 2.3 5.5 7.2 15.2 13.8 6x CAD Tool CPU Time (hour) >78 36 18 10 5 >15.6x

Conclusion Split-Row Threshold algorithm improves the error performance when compared with original Split-Row. Split-Row Threshold allows for high level of partitionings without losing significant error performance. Higher level of partitioning reduces the number of connections between check and variable processors. This results in a higher logic utilization, smaller and faster circuits. We can meet the demands of high speed applications while obtaining very low area when compared to standard decoding.

Support Special thanks Acknowledgements ST Microelectronics NSF Grant 430090 and CAREER award 546907 Intel SRC GRC Grant 1598 and CSR Grant 1659 Intellasys UC Micro SEM Special thanks Professor Shu Lin