Chap. 8 Datapath Units: Multiplier Design Prof. An-Yeu Wu Undergraduate VLSI Design Course Updated: June 12, 2002

Several Implementations of Multipliers Array Multiplier 2’s Complement Array Multiplier Serial Multiplier CSD Code String-encoding Multiplier Modified Booth-encoded Multiplier Implementation (Chap. 8.2.7.2) A. Y. Wu

6-by-6 Multiplication A. Y. Wu

Wallace-Tree Multiplication FA is a “one’s counter”: Take A, B, and C inputs and encodes them on SUM and CARRY outputs. A 1-bit full adder (FA) provides a 3:2 compression in the number of bits. A+B+C=2C+S A. Y. Wu

7-bit Wallace tree addition A. Y. Wu

Ex: 6×6 Wallace Multiplier A. Y. Wu

Example In a 32-bit multiplier, the maximum number of partial products is 32 and the compressions are： 32 → 22 → 16 → 12 → 8 → 6 → 4 → 3 → 2 => There are 9 Full-adder (FA) delays in the array c.f. Array multiplier (Booth-recoded) =16 partial products to be summed up. Can be used together with Booth-encoding scheme A. Y. Wu

Wallace Tree Multiplier MxN Booth-encoded multiplier (IEEE JSSC, vol.1,no.2, June 1993) A. Y. Wu

A typical delay distribution of the output of Wallace tree section A. Y. Wu

Extension 32-bits Wallace-tree multiplier has 9 FA delays in the array Questions: For a 64-bit multiplier, what is the minimum adder delay? Is there any way to reduce the delay by other compression scheme? A. Y. Wu

Approach: Using 4:2 compression adder The 4:2 compression (really 5:3) has three XOR delays in the SUM path. c.f.: Four XOR delays will be present if two adders are used A. Y. Wu

Referenced Paper A 54x54 regularly structured tree multiplier: IEEE Journal of Solid-State Circuits (vol. 27, no.9, 1992) A. Y. Wu

Chap. 8.2.7.2: Implementation of Booth-encoded Multiplier A. Y. Wu

Implementation: Radix-n Multiplication Modified Booth-recoding Values Xi-1 Xi Xi+1 OPERATION NEG ZERO TWO 0 0 0 add0 1 1 0 0 0 1 add2 0 0 1 0 1 0 sub1 1 0 0 0 1 1 add1 0 0 0 1 0 0 sub1 1 0 0 1 0 1 add1 0 0 0 1 1 0 sub2 1 0 1 1 1 1 add0 0 1 0 A. Y. Wu

16*16 Booth Multiplier A. Y. Wu

Array schematic A. Y. Wu

Array Floorplaning A. Y. Wu

First Rank Schematic A. Y. Wu

Booth decoding Schematic A. Y. Wu

Booth-Add-16 rank floorplan A. Y. Wu

Adder rank schematic A. Y. Wu

Booth gate A. Y. Wu

Array adder layout A. Y. Wu

Carry Propagate Adder A. Y. Wu

Homework #6 (Cancelled) Design an 8-bit Modified Booth-encoded (or String-encoding based) Wallace-tree Multiplier Draw the schematic diagram of your design. Verify your design first using C/C++ or Matlab programs. Write down the Verilog/VHDL code and perform simulation. Verify your Verilog/VHDL codes. That is,check your simulation results with the C/C++/Matlab results. Show your (1) Schematic (2) Source code (3) Simulation results in your report. Due date: June 28, 2002. A. Y. Wu