Subject Name: Embedded system Design Subject Code: 10EC74 Prepared By: Aswini N , M N Praphul & Navya Vipin (TE) Department: ECE Date: 10/11/14 11/14/2018

UNIT 3 11/14/2018

Dynamic RAM Overview, Chip Organization A Memory Interface in Detail TOPICS COVERED Classifying Memory Memory Interface ROM Overview Static RAM Overview Dynamic RAM Overview, Chip Organization A Memory Interface in Detail SRAM Design, DRAM Design DRAM Memory Interface The Memory Map, Memory Subsystem Architecture Basic Concepts of Caching Designing a Cache System, Dynamic Memory Allocation 11/14/2018

MEMORY MANAGEMENT In larger embedded applications there is a need of external memory apart from onboard memory. The memory subsystem is the place within an embedded system where instructions and data are stored. In embedded applications memory management is concerned with:- Static and dynamic allocation of memory. Avoiding dangerous allocation and minimizing/reducing overhead. Avoid deadlock situations. 11/14/2018

Internal Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only memory Not possible Masks Nonvolatile Programmable ROM (PROM) Erasable PROM (EPROM) Read-mostly memory UV light, chip-level Electrically Erasable PROM (EEPROM) Flash memory Electrically, block-level

MEMORY CLASSIFICATION Two general categories of memory RAM- Random Access Memory ROM- Read Only Memory 11/14/2018

MEMORY CLASSIFICATION RAM SRAM DRAM ROM PROM EPROM EEPROM 11/14/2018

MEMORY TYPES RAM- Random access memory DRAM- Dynamic RAM Any location in memory is visible for immediate access. Read and Write operation are comparable. Organized as bits, bytes or words. DRAM- Dynamic RAM Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged. 11/14/2018

MEMORY TYPES SRAM- Static RAM The stored charge will be leaked if it is not repeatedly refreshed. Used for larger memory systems. I/O is asynchronous wrt external clocks. SRAM- Static RAM Complex memory cell design Uses latch mechanism. No need of Refreshment. Used for higher speed memory systems since faster than DRAM. I/O is synchronous. 11/14/2018

MEMORY TYPES- SRAM 11/14/2018

MEMORY TYPES ROM- Read only Memory PROM- Programmable ROM ROM can only be read. Read operation is faster than Programming the ROM(writing). Organized as bits, bytes or words. PROM- Programmable ROM The device can be programmed one time using a programming device. EPROM- Erasable PROM ROM can be re programmed by erasing the program by keeping the device under uv light for specific time. 11/14/2018

MEMORY TYPES EEPROM- Electrically Erasable PROM FLASH Memory Here for program is erased electrically via a programming device. FLASH Memory Flash memory was developed from EEPROM. The advantage is that it can be reprogrammed in situ ( No need to remove the device from the circuit.) 11/14/2018

A GENERAL MEMORY INTERFACE Array as a simple Memory Model Index 1234 1 3456 2 FACE 3 DEAD 4 EAD3 5 BADDE 6 FEAD 7 7654 Data 11/14/2018

A General Memory Interface Memory Interface diagram showing Address, Data and Control Lines. 11/14/2018

Terminologies used in memory 11/14/2018

ROM Architecture Along with Address and Data lines, ROM requires a chip select. 11/14/2018

ROM Read Operation 11/14/2018

Memory Mapping 11/14/2018

SRAM Design- An Example System Specification- SRAM System that can store 4K X 16 bit words. Assumption 8 Address lines and 8 Data Lines available. Requirement- For 4KX 16 bit memory we need 12 Address lines and 16 data lines. Additional Requirements- Chip select (CS) and Output Enable (OE). 11/14/2018

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SRAM Write 11/14/2018

SRAM Read 11/14/2018

DRAM DESIGN/MEMORY INTERFACE Assumption- 4M word memory chip organized as 4K rows and 1K columns. One row refreshed at a time and refreshment management done outside the chip. Need of 12 row address bits and 10 column address bits. Utilize a two phase clocking scheme derived from 50MHz source. 11/14/2018

DRAM DESIGN/MEMORY INTERFACE Refresh Interval Timer Refresh Interval 128 256 9 bit Binary counter 25MHz Refresh active 11/14/2018

Memory Subsystem Architecture 11/14/2018

Concept of Caching  CPU cache is a cache used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels (L1, L2 etc.) 11/14/2018

Concept of Caching 11/14/2018

Cache Systems –Direct Mapping Each location in RAM has one specific place in cache where the data will be held. 11/14/2018

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Associative Cache mapping 11/14/2018

Memory Allocation Static Memory Allocation – Initially we will be alloting a specific memory. The program knows the actual data location. Dynamic Memory Allocation- Memory is assigned during run time. 11/14/2018