CPE/EE 428, CPE 528 Testing Combinational Logic (5) Department of Electrical and Computer Engineering University of Alabama in Huntsville

Test Generation: The Podem Algorithm What you know The basic pieces of automatic test generation (ATG) justification, propagation, implication, etc. D-frontier J-frontier The D algorithm What you don’t know A better way — Podem Today Podem 14/11/2018 VLSI Design II

Test Generation: The D Algorithm if (imply_and_check() == FAIL) return FAIL if (error not at primary output) { if (D-frontier == Ø) return FAIL repeat { select an untried gate (G) from D-frontier c = controlling value of G assign c’ to every input of G with value x if (D-Alg() == SUCCESS) return SUCCESS } until all gates from D-frontier tried return FAIL} if (J-frontier == Ø) return SUCCESS select a gate G from the J-frontier select an input (j) of G with value x, assign c to j assign c’ to j /* reverse decision*/ } until all inputs of G are specified return FAIL Decorate design with all known values. Check for inconsistencies. Push D to a primary output Once at primary output, justify all values needed to have D on the primary output 14/11/2018 VLSI Design II

From Last Time… all x’s c=1, b=1 j a Decision Tree D’ g h=1 1 b k 1 c Decision Tree D’ h=1 1 1 c-sa0 D D’ D j=0 a=1 1 d=0 decisions implications comments c=1,b=1,g=f=D’ activate fault, unique D drive h=1 i=D prop through i. j,k=Df; h=Jf a=1 j=D’, k=1 prop through j. Df = null. backtrack (a = x) j=0 a=0, k=D prop through i, fault at output d=0 justify h 14/11/2018 VLSI Design II

New concept to add x-path The D-frontier in the circuit below is hopeless. There is no path to a primary output An x-path is a circuit path along which all of the gate outputs have value x If a gate in the D-frontier does not have at least one x-path to a primary output, the D cannot propagate to the output through this gate. Don’t bother considering this gate for propagation Drop it from the D-frontier (however, it may come back) x 1 D D-frontier 14/11/2018 VLSI Design II

Testing Digital Systems: Podem Podem — Path-oriented decision making Only uses forward implication manipulates primary inputs directly — very goal oriented No J-frontier or consistency check since only the primary inputs are specified with values there is no inconsistency the values might not be correct (i.e. the ones you want), but the implied values in the circuit are always consistent Basic iterative flow determine an objective e.g. justifying a line or propagating a D find a primary input to control the line or the propagation set primary input and do forward implication is everything cool? yes, no? 14/11/2018 VLSI Design II

PODEM Algorithm PODEM – Path-Oriented DEcision Making algorithm solves the problem of reconvergent fanout and allows multipath sensitization Four basic steps: Objective, Backtrace, Implication, D-frontier Objective Pick an objective to set a node to a value Backtrace Backtrace to a PI and set it to a value that will help meet the objective Implication simulate the network to calculate the effect of fixing the value of PI. If there is no possibility of sensitizing a path to a PO, then retry by reversing the value of PI that was set in step 2 and simulate again. D-frontier Update D-frontier and return to step 1. Stop if the D-frontier reaches a PO. 14/11/2018 VLSI Design II

Podem: determining an objective Given: we want to test line l s-a-v or propagate a fault to a primary output There are only two objectives that can result Objective() if (line l is an x) return (l , v’) select gate G from D-frontier select input j from G having value x c = controlling value of G return (j, c’) In both cases — the objective is to justify a line — a line and value are returned objective is justifying fault site to v’ objective is propagating fault along D-frontier to primary output 14/11/2018 VLSI Design II

Podem: the difference Given an objective we must find a primary input to control to meet it With the D algorithm, we didn’t look for PIs Rather the D-alg put c’ on the other x inputs of the gate and assumed that it will work out later Backtrace — The objective is to justify a line to a certain value step backward through gates until a PI is found at each gate, select a gate input to follow only keep track of inversions, no values assigned return a primary input and the value to set it to setting the PI to the value is not guaranteed to work! 14/11/2018 VLSI Design II

Podem: Backtrace Backtrace (k, vk) v = vk while (k is a gate output) { i = inversion of k select an input (j) of k with value x v = v  i k = j } return (k, v) while we’re not at a PI Determine what the input should be based on the inversion. Step backward All this does is find a PI and a value to set it to 14/11/2018 VLSI Design II

Podem: Backtrace Backtrace example — set f to 1 Select in alphabetical order … Are these values for primary inputs enough?, OK? need to do forward implication and further checking i.e. they may fanout and block the D-frontier a b c d e f … f=1 14/11/2018 VLSI Design II

Podem: Backtrace Another example: make this a 1 14/11/2018 make this a 1 14/11/2018 VLSI Design II

Podem: the main algorithm if (error at primary output) return SUCCESS — you win, party time if (test not possible) return FAIL (k, vk) = Objective() (j, vj) = Backtrace (k, vk) imply (j, vj) if (Podem == SUCCESS) return SUCCESS imply (j, v’j) imply (j, x) return FAIL } Pick a gate from D-frontier or activate fault Find an input success — error is at PO, or we got another gate from the D-frontier and (recurse, recurse, …) got error to PO. “test not possible” D-frontier == , or is expected to become  14/11/2018 VLSI Design II

Podem: the main algorithm if (error at primary output) return SUCCESS — you win if (test not possible) return FAIL (k, vk) = Objective() (j, vj) = Backtrace (k, vk) imply (j, vj) if (Podem == SUCCESS) return SUCCESS imply (j, v’j) imply (j, x) return FAIL } Oops, forward implications failed. Assign complement to input success — error is at PO, or we got another gate from the D-frontier and (recurse, recurse, …) got error to PO. Oops, another failure. Probably D-frontier went east. 14/11/2018 VLSI Design II

Testing Digital Systems: Podem b c d e f g h i j k l m n d’ e’ f’ s-a-1 14/11/2018 VLSI Design II

An example Decision Tree a = 0 1 a = 0 a b d e f g h i j k l m n d’ e’ f’ s-a-1 Objective PI assignment Implications Comments a_branch = 0 a = 0 h = 1 D-frontier becomes {g} a_branch = D’ 14/11/2018 VLSI Design II

An example Decision Tree a = 0 b = 1 c = 1 d = 1 e = 0 e = 1 f g h i j k l m n d’ e’ f’ s-a-1 b = 1 1 D’ c = 1 1 1 D d = 1 1 D’ 1 e = 0 e = 1 Objective PI assignment Implications Comments k = 1 e = 1 e’ = 0, j = 1 D-frontier becomes {m, n} k = D’, n = x reverse decision 14/11/2018 VLSI Design II

An example Decision Tree a = 0 b = 1 c = 1 d = 1 e = 0 e = 1 f = 1 g h i j k l m n d’ e’ f’ s-a-1 b = 1 1 D’ c = 1 1 D 1 D d = 1 1 D’ 1 c 1 e = 0 e = 1 1 D’ f = 1 Objective PI assignment Implications Comments l = 1 f = 1 f’ = 0, l = 1 m = D’, n = D Party time! 14/11/2018 VLSI Design II

Another example G-sa1 j a g b k G c f d i e h OBJ, PI implications comments 14/11/2018 VLSI Design II

Summarizing the process set of faults for circuit X X X X define fault model X X X X select target fault no more faults: done generate test for target — 100 fault simulate 1 X X X discard detected faults X 14/11/2018 VLSI Design II

Podem Summary Summary and comparison to D More of a direct approach “what PIs can I wiggle to reach my objective” backtracking arises only to change a primary input’s value. In the D algorithm, any gate input inconsistency could cause a backtrack. There are fewer PI’s than gate inputs! Inconsistency doesn’t happen (from backtrace) always going forward from primary inputs however, setting inputs can cause x-path to output to go away No J-frontier Simplified recursive state changes state in this algorithm is the PI values everything else can be calculated through forward implication Original comparison data showed faster runtimes. Progression of techniques from D —> Podem 14/11/2018 VLSI Design II

Selecting gates and inputs D and Podem run for a long time What can be done to improve the run time? consider the “select one input” and “select one gate” one path might be better than another … repeat { select an untried gate (G) from D-frontier c = controlling value of G assign c’ to every input of G with value x if (D-Alg() == SUCCESS) return SUCCESS } until all gates from D-frontier tried return FAIL} which one? 14/11/2018 VLSI Design II

Controllability Illustrative examples Controllability — A measure of how difficult is it to justify a line justify this to a zero b a Obviously, b is more controllable than a. … a b justify this to a zero Obviously b, has fewer side-effects than a and may lead to fewer problems with reconvergent fanout. Can controllability be quantified? 14/11/2018 VLSI Design II

What’s the cost of observing a? What’s the cost of observing a? Observability Illustrative examples Observability — A measure of how difficult it is to propagate a value to a primary output? Includes costs for controllability because some lines “need justified” What’s the cost of observing a? a a What’s the cost of observing a? Can observability be quantified? 14/11/2018 VLSI Design II

Notation: Cv(l) is the cost of setting line l to v. Controllability Notation: Cv(l) is the cost of setting line l to v. Two situations The cost of setting f to 0 is the minimum of the costs of setting each of the inputs to 0 C0(f) = min{ C0(a), C0(b), C0(c) } The cost of setting f to 1 is the sum of the costs of setting all of the inputs to 1 C1(f) = C1(a) + C1(b) + C1(c) a b c f 14/11/2018 VLSI Design II

Notation: Cv(l) is the cost of setting line l to v. Controllability Notation: Cv(l) is the cost of setting line l to v. Generally In terms of controlling value c and inversion value i Consider the case where one of the inputs has controlling value c: Cci(f) = min{ Cc(a), Cc(b), Cc(c) } Gate output Consider the case where all of the inputs must have non-controlling value c’ Cc’i(f) = Cc’(a) + Cc’(b) + Cc’(c) 14/11/2018 VLSI Design II

What inputs are needed to justify a to 0? How is this applied? Approach The cost of setting an input is defined as 1 Proceed from the inputs to the line in question. The cost of setting f to 0 — C0(f) = min{C1(b), C1(a)} The cost of setting a to 0 ? 1 b a f What inputs are needed to justify a to 0? 14/11/2018 VLSI Design II

Controllability Well, there are some anomalies What’s the cost of setting f to1? C1(f) = C1(a) + C1(b) C1(b) = C0 (a) C1(f) = C1(a) + C0 (a) But that’s impossible and the cost should be infinity OK, it’s off-the-wall, but maintain perspective! the point is that these methods consider only the structure the cost of “doing all of the logic” to figure them out is high higher than doing a bad job of “selecting a gate” we don’t want the cost of selecting the correct path to be greater than the penalty for picking the wrong path f a b 14/11/2018 VLSI Design II

Observability Back to the AND gate What’s the cost of observing a? you need to control b and c to one you need to observe f Thus: O(a) = C1(b) + C1(c) + O(f) How about a fanout from a stem? the cost of observing a stem is the minimum of observing its branches O(q) = min{ O(r), O(s) } a b c f … … q r s 14/11/2018 VLSI Design II

Observability Approach The cost of observing a primary output is defined to be 0 The circuit is traversed backward from the outputs Assuming a = D, what values will be at the POs? a PO PO Let’s say this is the D frontier — which way do we go? 14/11/2018 VLSI Design II

Cost of Testability Can we calculate how hard it is to test a fault? the cost of activating the fault (controlling it), plus the cost of observing the fault (propagating it). Why do this? figure out what’s hard to test, and redesign the circuit. a-sa0 a 14/11/2018 VLSI Design II

Summary These costs are heuristics But, the magnitudes have little physical meaning — # of inputs they are meant to be easily-calculated indicators of: which gate to select from the D-frontier which gate input to select for backtracing or J-frontiering they can’t be more difficult to calculate than actually selecting the wrong gate or gate input. thus the logic function is not considered But, they are important for trimming the search space of the ATG algorithms 14/11/2018 VLSI Design II