Architectural Features

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Presentation transcript:

Architectural Features XC9500 Architectural Features

XC9500 Architectural Features Predictable, all pins fast, PAL-like architecture FastCONNECT switch matrix provides 100% routing with very high device utilization Flexible function block 36 inputs with 18 outputs Product term expansion with up to 90 product terms per macrocell Global and product term clocks Global and product term output enables Global and product term set/reset signals 6 2

Programming Controller I/O - Global Tri-States XC9500 Architecture 3 JTAG Controller In-System Programming Controller JTAG Port Function Block 1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O I/O - Global Clocks Function Block 3 3 I/O - Global Set/Reset 1 Function Block n I/O - Global Tri-States 2 or 4 5 1

XC9500 Function Block Flexible “36V18” PAL Blocks 4

FastCONNECTTM Switch Matrix 100% routable, high-speed connections 5

XC9500 Macrocell Powerful, flexible macrocell logic: 1 to 90 p-terms Individual p-term or global signals for clock, OE, set, reset 6

XC9500 P-Term Allocation Example #1 7

Complex P-Term Allocation Example #2 8

XC9500 P-Term Allocator Logic Flexible, bi-directional cascade / bypass capability 9

XC9500 Clock, Set/Reset Capability 11

XC9500 OE Capability 12

XC9500 Power-Up Characteristics 3.8 V (Typ) 0 V No Power Quiescent State User Operation VCCINT Initialization of User Registers Well-behaved quiescent characteristics: JTAG, I/O pins, internal operation disabled 10 kohm pull-up resistors activated on each user I/O pin 13