11/14/2018 Changing Paradigms - Fast-Turn RF and Mixed-Signal IP IEEE Annual EDP-2001 Workshop session on Analog/MS Design Flows James Spoto Enablix.

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Presentation transcript:

11/14/2018 Changing Paradigms - Fast-Turn RF and Mixed-Signal IP IEEE Annual EDP-2001 Workshop session on Analog/MS Design Flows James Spoto Enablix Solutions April 10, 2001

Communications Systems Challenge 11/14/2018 Communications Systems Challenge Today, the wireless & optical Industry is limited in ability to deliver timely RF & mixed signal based products Scarce skill set No standard/commercial design platforms & IP Long custom development cycle with many spins Expensive (people, non-reuse, lab) Not available (until now!) in pure-play foundries REAL -TIME AND COST GOALS DICTATE ASSEMBLY TODAY ASSEMBLY LANGUAGE IS ERROR PRONE NO ERROR CHECKING HARD TO FIND ASSEMBLY PROGRAMMERS HAMMER AND CHISEL VS. WORD PROCESSOR NO PRODUCT EXISTS TO ALLOW HIGH LEVEL LANGUAGE RF and mixed signal design cycles are pacing wireless & optical product Time-to-Market 11/14/2018

Costly, Risky,Lengthy Custom Design IP Hierarchy Digital RF/Mixed-Signal CDMA/GSM/TDMA Dig BB Bluetooth/802.11a,b BB Ethernet/ADSL/CBL data pumps and controllers CDMA/GSM/TDMA MS BB CDMA/GSM/TDMA Radios Ethernet/ADSL/Cable Phys Differentiating IP Costly, Risky,Lengthy Custom Design ARM/MIPS/DSP cores Datapath/Memory Compilers Cell Libs/design platforms Enabling IP & Design Platform No Significant Commercial Suppliers Growing List of Commercial Suppliers Semi Foundries 11/14/2018 RF/Mixed-Signal Subsystems Driving Costs and Schedules

RF/Mixed-Signal R&D Investment Total R&D Investment is 15% to 20% of IC Shipments % of Total 50% 25% CDMA/GSM/TDMA MS BB CDMA/GSM/TDMA Radios Ethernet/ADSL/Cable Phys Differentiating IP A/Ds, RF Transceivers, PLLs Filters, Amps, Mixers, VCOs, S/Hs Design Platform (Tools,Lib,Flow) Enabling IP & Design Platform Semi Foundries Design platforms and Enabling IP make up over 50% of R&D costs 11/14/2018

Design Platform Architecture Design Capture & Synthesis Exploration, Optimization & Simulation Physical Design Final Design Verification RF/MS Methodology & Flow IC Product Specification Finished Product Tape-out Symbols & Component Descriptions Spice Models Interconnect & Device Parasitics Device Generators & Layout Options LVS, DRC, Ext Tech Files Platform IP Component Representations Schematic Capture Circuit Simulation & Waveform Tool Analog P&R & Layout Editor DRC, LVS & Extraction Tools Industry Leading EDA Tools 11/14/2018

Complex Generators - Differential Inductor Parameterized Design Input Equivalent Circuit Model - Automatically Generated Layout - Automatically Generated 11/14/2018

Package Models 11/14/2018

Portable and Configurable IP Components Created in days vs months! Parameterized Device Generators w=f1(gain,bw,sr…) l=f2(gain,bw,sr…) Application Cell Technology Topology Gain Slew Rate Bandwidth Settling Time Input Swing Noise Output Swing Power PSRR CMRR Selection--------------------------------------------------------- Specification---------------------------------------------------- Performance------------------------------------------------------ AC Transient Swing Disto OK Cancel Apply Help Specifications Out Input Vref R D A C CDAC SAR Speed #Bits Floorplan Tiler Gain = F(Speed, #bits) BW = F(Speed, #bits) SR = F(speed, #bits) Mapping Modules Foundry Specific Technology Data Device level P&R, Compaction 11/14/2018

Generated PLL* Spec 2 Weeks Multi-Phase PLL TSMC 0.25um 25MHz-165MHz Application - Digital Video GDSII Data Sheet Simulations Models LVS Netlist *Courtesy and Copyright Portability,Inc.©2001. All rights reserved 11/14/2018