EE 584 Homework #1 Inverter Design

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Presentation transcript:

EE 584 Homework #1 Inverter Design Stan McVay October 15, 2002

Schematic Design – Design Architect

Digital Simulation – Quicksim II Confirmed digital functionality of the circuit

Layout Design – IC Station

Layout Design – Verification and Extraction DRC Check used several times to find Design Rule violations LVS Passed after layout was completed: Parasitic and Distributed extractions completed. Seemed to match well to tutorial (order of magnitude).

Analog Simulation - Accusim Confirmed functionality was correct:

Analog Simulation - Accusim Rise and Fall Times were significantly different than the tutorial values: These values are about ¼ of the values in the tutorial. Could find no obvious reason for this.