A 60-GHz Variable Delay Line on CMOS for Steerable Antennae in Wireless Communication Systems C. M. Ta, E. Skafidas, R. J. Evans, and C. D. Hoang† NICTA, Dept. of Electrical and Electronic Eng., The Univ. of Melbourne †Dept. of Telecommunications, Ho Chi Minh City Univ. of Technology Hello and welcome to my talk on the design of a 60 ghz variable delay line on CMOS for steerable antennae in wireless communication systems.

Wireless communications at 60 GHz Outline Wireless communications at 60 GHz Phased array antennae Design of the variable delay line Design of a π-segment Design and optimization of the varactor Results Conclusions I will start with an introduction on wireless communications at 60 GHz which will explain why we need steerable antennae or phased-array antennae at 60 ghz. Then, I will move to the design of the variable delay line which is a critical component for the phased-array. I will close my talk with the results and conclusions. November 14, 2018 CCECE 2008

60 GHz wireless communications Unlicensed band 7 GHz of bandwidth worldwide Multi-Gbps wireless communications Low power Portable applications Low cost CMOS High path loss 88 dB free space loss at 60GHz and 10 m distance Additional attenuation due to oxygen absorption Phased-array antenna system We want to use 60 GHz for wireless communications because we are looking for method to transmit data wirelessly at multi-giga-bit-per-second data rate to accommodate applications such as Wireless Personal Area Network and High-Definition Multimedia Interface (HDMI). The 60-GHz spectrum is a good solution for these applications. There is 7 GHz of bandwidth around 60 GHz has been allocated in US, Europe, Japan for unlicensed used. This largest ever released frequency band is much wider than those used in 802.11 networks these day. So If we can make use of this band, we can transmit and receive data at multi gigabit per second speed. The advantage of 60 GHz band in particular and the millimeter-wave band from 30-300 GHz is that the wavelength is very short which allow high level of integration including Filters, Passive balun, even Antennas and phased-array. The reason that a smart antenna system is required for 60-GHz wireless communications is that transmission over the air at 60 GHz is very lossy. The smart antenna system will improve the antenna gain in both transmitter and receiver and can counter the effect of interferers. Low cost: Low-cost and high-integration process. CMOS is chosen. November 14, 2018 CCECE 2008

Steerable antennae Transmitter: focus output power Receiver: improve SNR, reject interferers The idea is to implement a transmitting and receiving system which can transmit and receive signal wisely. The transmitter will transmit only in the direction that the intended receiver is located and the receiver only try to pick up the signal in a certain direction and reject interferers from other directions. This can be done with a steerable antennae system or phased-array system. To implement a steerable antenna, we need a mechanism to control the phase of the signals that excite individual antenna. Ideally, we need a variable time-delay element. However, when the signal of interest is narrowband, the variable delay element can be replaced by phase shifter which is the reason why this system is usually referred to as phased-array system. In the rest of the talk, I will present the design of a true variable time-delay element on CMOS technology. Important characteristics of the variable delay line are its impedance, insertion loss, phase tuning range, group delay which are going to be presented. November 14, 2018 CCECE 2008

Variable delay line Cascade of multiple π-segments The variable delay line is based on a synthesis transmission line which consists of multiple pi-segments in series. It has an input and an output. The amount of phase shift is controlled by Vctrl. Notice that even though this is a true delay line, I am still using the term phase shift to describe its characteristic. This is because there is a relationship between phase shift and time delay. This is the detail schematic of a pi-segment which include a transmission line which is used as an inductor L and two varactor which are variable capacitors. The biasing voltage Vg is applied to the gate of the varactor and the control voltage Vctrl is applied to the drain of the varactor. By changing Vctrl, we change the value of C and therefore change the amount of phase shift introduce by the pi-segment. The questions now are how to choose the value of L, C, Vg, and Vctrl and how to implement the varactor effectively at 60 GHz. Cascade of multiple π-segments Distributed design for wideband operation November 14, 2018 CCECE 2008

Design of a π-segment Each π-segment is matched to Z0 L (66 pH) is realized as a transmission line C (27 fF) is realized as a varactor How to find the value of L and C is presented here. Let’s look at a simple pi-segment like this. To ensure that the VDL has the desired characteristic impedance Z0, let say 50 Ohm, each pi-segment is design such that its input and output impedance is 50 if the other end is terminated by 50 as shown in this picture. By doing so, when multiple pi-segments are connected in series, the power can be transferred from one segment to the other without any reflection loss. If we write down the equation for the input impedance of this network at force it to be 50 we end up with the following relationship between L, C, F, and Z0 which must be hold for a perfect impedance match. If we use 50 Ohm for Z0 and 60G for f, the relationship between L and C is shown in this graph. In this design, I choose L equal to 66 pH which is realized as a 200um transmission line. And I choose the value of C is 27 fF which is the average value of the varactor. November 14, 2018 CCECE 2008

MOS varactor optimization Design parameters Finger width Finger length Number of fingers Capacitance tuning ratio Affect the phase tuning range Need to reduce Cf  single finger device Quality factor Affect the insertion loss Need to reduce Rpc and Rs  multiple-finger device (6 x 3) x (0.24um x 1um) The varactor is an NFET built in an n-well with its short and drain shorted together. Several parameters of the MOS varactor need to be decided to optimize its capacitance tuning ratio and quality factor. These parameters include the number of the fingers and the length and width of each finger. The capacitance tuning ratio is the ratio of the maximum and minimum capacitance of the varactor and this quantity needs to be maximize in order to maximize the phase tuning range of the delay line. If we look at the model of the varactor, we see that the capacitance of the varactor comprises of two component, a controllable portion, Cvar, and a parasitic, which means uncontrollable, portion Cf. To maximize the capacitance tuning ratio, we need to minimize Cf. Because Cf is the fringing capacitance between the gate and the drain of the varactor, we can minimize Cf by laying out the varactor as a single finger device since this layout result in a minimum perimeter of the gate. The quality factor of the varactor needs to be maximized to reduce the insertion loss of the delay line. To do so, we have to minimize the resistance of the polysilicon gate, Rpc, and the resistance of the silicon substrate, Rs. From the layout perspective, Rpc and Rs can be reduced by laying out the varactor as a multiple-finger device. We can see that there is a trade-off must be done here because if we want high capacitance tuning ratio, we should have a single finger device, if we want high quality factor, we should have multiple-finger device. By running many simulation and compare the output, we decide that our varactor will have 18 fingers, each finger is 0.24um length and 1 um width. This plot show the quality factor and the effective capacitance of the varactor at different biasing voltages. November 14, 2018 CCECE 2008

Layout considerations Here is the layout of the designed variable delay line. An important factor when design on CMOS is to minimize the area of the layout as the cost of the chip is proportional to its area. In this design, efforts have been made to keep the layout as compact as possible without sacrificing the ability to extend the design for larger phase tuning range. By laying out each pi-segment in an S-shape, multiple instance of the pi-segments can be easily cascaded to form the variable delay line. As shown here, a five-segment VDL is laid out and measured about 430um by 220 um only. Because each pi-segment can provide a certain range of phase tuning, if larger phase tuning range is required, all we have to do is add more pi-segment to the design. Due to the S-shape of the pi-segment, there might be some degree of electromagnetic coupling between successive transmission line. For example, between this one an this one, et cetera. To prevent this undesirable coupling, side-shielded microstrip lines are use to implement the inductor of each pi-segment. The side shield metal will stop the coupling between different microstrip lines. Then, for testing purpose, RF test pads are added to the input and output of the VDL. To make sure the whole structure is still matched to 50-Ohm, two impedance matching network is inserted between the VDL and the RF test pads to tune out the capacitance of the test pads. Compact, extensible layout Side-shielded microstrip line Impedance matching network for testing purpose November 14, 2018 CCECE 2008

Performance Maximum phase shift of 100 degrees Here is the performance of the variable delay line. With the control voltage chagned from 0.5 to 1.2 V and the gate voltage, Vg is fixed at 0.7 V, the phase shift is changed from 0 to 100 degrees. At maximum phase shift, the insertion loss is also maximized and is about 6 dB. Maximum phase shift of 100 degrees Maximum insertion loss of 6 dB November 14, 2018 CCECE 2008

Performance (cont’d) Wideband matching to 50-Ohm termination Less than 4ps group delay variation around 60-GHz The impedance matching and group delay shows that the variable delay line is very wideband. Its impedance matches well to 50 Ohm for frequency from 20 GHz to over 100 GHz. Around 60 GHz, the group delay is less than 4ps for all control voltages from 0.5 to 1.2 V. November 14, 2018 CCECE 2008

A variable delayed line on CMOS Millimeter-wave operation Conclusions A variable delayed line on CMOS Millimeter-wave operation Good impedance matching Constant group delay In conclusion, a variable delay line has been designed on CMOS technology for millimeter-wave operation. It has good impedance matching to 50 Ohm and presents constant group delay. November 14, 2018 CCECE 2008

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