Marek Morawski, Hanna Rothkaehl Space Research Centre PAS

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Presentation transcript:

Marek Morawski, Hanna Rothkaehl Space Research Centre PAS ESA EJSM/JGO Radio & Plasma Waves Instrument Digital Processing Unit (architecture and design concept) Marek Morawski, Hanna Rothkaehl Space Research Centre PAS

DPU Architecture

Board Supervisor Unit Do we need floating point arithmetic processor ?

BSU – Main Tasks The BSU features should cover all functions required for minimum instrument functionality Internal mode control Tele command (TC) verification, validation and execution Switching and commanding of measurements module Data collection and buffering Telemetry (TM) packet formatting and sending Housekeeping data collection

Clock Management Unit The Clock Management Unit is dedicated to provide stable clock source for BSU and SPU modules.

Clock and Module Control I/F Maximum clock frequency up to 100 MHz (Power consumption !!!) The same reference & transmission clock for all Multi-Drop LVDS control data transmission common for all modules Is redundancy needed?

Memory Unit Code loader & Exception service (*) Application software code (*) Application data structures (*) Configuration and calibration tables Software patches Configuration bit streams of SPU FPGA Telemetry packet buffer (*) Correct Always & Scrubbing

Housekeeping Acquisition The analogue to digital conversion is based on comparison of measured value to generated Sigma-Delta ADC embedded in BSU FPGA. (RC net outside) 44031RC Precision Epoxy NTC Thermistor (YSI 44908 ) Phobos-Grunt –JAN 2011 RELEC – End of 2011 Reference Ur = 2.5V Voltage Ux = 0 to 5.0V Temperature T = -60°C to 100 °C (TBC)

Signal Processing Unit Implementation of RAM configured FPGA (Xilinx) Part Main Feature TID SEL [krads(Si)] MeVcm2/mg XQR4VFX60 60k logic cells 2 PowerPC ~4Mb RAM 300 100.0 XQR4VSX55 55k logic cells 512 DSP slices ~5.7 Mb RAM Possibility of reconfiguration during the flight Algorithm hardware implementation Wide portfolio of IP modules TMRTool (triple logic)

Data exchange block diagram In case of „Signal Processing Unit” failure (or switched off) the data stream could be caught by BSU (reduced performance)