Technology and Historical Perspective: A peek of the microprocessor Evolution 11/14/2018 cpeg323\Topic1a.ppt.

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Presentation transcript:

Technology and Historical Perspective: A peek of the microprocessor Evolution 11/14/2018 cpeg323\Topic1a.ppt

Moore’s Law and Headcount Along with the number of transistors, the effort and headcount required to design a microprocessor has grown exponentially 11/14/2018 cpeg323\Topic1a.ppt

Intel 486™ DX CPU Design 1986 – 1989 25 MHz, 33 MHz 1.2 M transistors 1.0 micron 5 stage pipeline Unified 8 KByte code/data cache (write-through) First IA-32 processor capable of executing 1 instruction per clock cycle 11/14/2018 cpeg323\Topic1a.ppt

Pentium® Processor Design 1989 – 1993 60 MHz, 66 MHz 3.1 M transistors 0.8 micron 5 stage pipeline 8 KByte instruction and 8 KByte data caches (writeback) Branch predictor Pipelined floating point First superscalar IA-32: capable of executing 2 instructions per clock 11/14/2018 cpeg323\Topic1a.ppt

Pentium® II Processor Design 1995 – 1997 233 MHz, 266 MHz, 300 MHz 7.5 M transistors 0.35 micron 16 KByte L1I, 16 KByte L1D, 512 KByte off-die L2 First compaction of P6 microarchitecture 11/14/2018 cpeg323\Topic1a.ppt

Pentium® III Processor (Katmai) Introduced: 1999 450 MHz, 500 MHz, 533 MHz, 600MHz 9.5 M transistors 0.25 micron 16 KByte L1I, 16 KByte L1D, 512 KByte off-chip L2 Addition of SSE instructions. SSE: Intel Streaming SIMD Extensions to the x86 ISA 11/14/2018 cpeg323\Topic1a.ppt

Pentium® III Processor (Coppermine) Introduced: 1999 500MHz … 1133MHz 28 M transistors 0.18 micron 16 KByte L1I, 16 KByte L1D, 256KByte on-chip L2 Integrate L2 cache on chip, It topped out at 1GHz. 11/14/2018 cpeg323\Topic1a.ppt

Pentium® IV Processor Introduced: 2000 1.3GHz … 2GHz … 3.4GHz 42M … 55M … 125 M transistors 0.18 … 0.13 … 0.09 micron Latest one: 16 KByte L1I, 16 KByte L1D, 1M on-chip L2 Very high clock speed and SSE performance 11/14/2018 cpeg323\Topic1a.ppt

Intel® Itanium® Processor Design 1993 – 2000 733 MHz, 800 MHz 25 M transistors 0.18 micron 3 levels of cache 16 KByte L1I, 16 KByte L1D 96 KByte L2 4 MByte off-die L3 Superscalar degree 6, in-order machine First implementation of 64-bit Itanium architecture 11/14/2018 cpeg323\Topic1a.ppt

Intel® Itanium 2® Processor Introduced: 2002 1GHz 221 M transistors 0.18 micron 3 levels of cache 32 KByte I&D L1 256 KByte L2 integrated 1.5MByte L3 Based on EPIC architecture Enhanced Machine Check Architecture (MCA) with extensive Error Correcting Code (ECC) 11/14/2018 cpeg323\Topic1a.ppt

Cache Size Becoming Larger and Larger 2002: Itanium-2 1993: Pentium 1997: Pentium-II Level 1: 16K KByte I-cache, 16 KByte D-cache Level 2: 256 KB Level 3: integrated 3 MB or 1.5 MB 8 KByte I-cache and 8 KByte D-cache 16 KByte L1I, 16 KByte L1D 512 KByte off-die L2 11/14/2018 cpeg323\Topic1a.ppt

Motorola’s PowerPC 604 Pentium 11/14/2018 cpeg323\Topic1a.ppt

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Technology Progress Overview Processor speed improvement: 2x per year (since 85). 100x in last decade. DRAM Memory Capacity: 2x in 2 years (since 96). 64x in last decade. DISK capacity: 2x per year (since 97). 250x in last decade. 11/14/2018 cpeg323\Topic1a.ppt

In addition: - heat problem - design complexity Data source: http://www.spec.org/cpu2000/results/cint2000.html http://www.geek.com/procspec/procspec.htm http://www.bayarea.net/~kins/AboutMe/CPUs.html Main observation: application of additional resources yields diminishing return in performance In addition: - heat problem - design complexity 11/14/2018 cpeg323\Topic1a.ppt

Pentium M Thermal Maps from the Pentium M obtained from simulated power density (left) and IREM measurement (right). Heat levels goes from black (lowest), red, orange, yellow and white (highest) Figures courtesy of Dani Genossar and Nachum Shamir in their paper Intel ® Pentium ® M Processor Power Estimation, Bugdeting, Optimization and Validation published in the Intel Technical Journal, May 21, 2003 11/14/2018 cpeg323\Topic1a.ppt

What Is Next ? Move to “multiprocessor on a chip” ? cooler simpler cheaper … 11/14/2018 cpeg323\Topic1a.ppt

Alternatives: Multi-Core-On-A-Chip Driven by technology reality (too hot and too complex) Examples: Intel multi-core roadmap (see EE Times) AMD Opteron Outcomes from HPCS projects from DARPA IBM Multi-Core Chips: The CELL product - IBM, Sony, Toshiba IBM/ETI Cyclops Product Others (e.g. Clearspeed, etc.) Box vendors are beginning adapting multi-core chips 11/14/2018 cpeg323\Topic1a.ppt

IBM Power5 Multicore Chip Technology: 130nm lithography, Cu, SOI Dual processor core 8-way superscalar Simultaneous multithreaded (SMT) core Up to 2 virtual processors per real processor 24% area growth per core for SMT Natural extension to POWER4 design Courtesy of “Simultaneous Multi-threading Implementation in POWER5 --IBM's Next Generation POWER Microprocessor” by Ron Kalla, Balaram Sinharoy, and Joel Tendler of IBM Systems Group 11/14/2018 cpeg323\Topic1a.ppt

Quad AMD Opteron™ AMD Opteron™ 940 mPGA AMD Opteron™ 940 mPGA 200-333MHz 9 byte Reg. DDR 8-G DRAM AMD Opteron™ 940 mPGA 200-333MHz 9 byte Reg. DDR 8-G DRAM 200-333MHz 9 byte Reg. DDR AMD Opteron™ 940 mPGA VGA PCI Graphics AMD-8111TM I/O Hub SSL Encryption TCP/IP off load engine Legacy PCI FLASH LPC SIO Management 100 BaseT Management LAN SPI 3.0 interface USB1.0,2.0 AC97 UDMA133 10/100 Ethernet Modular Array ASIC 10/100 Phy GMII to OC-12 or 802.3 GigE NIC 11/14/2018 cpeg323\Topic1a.ppt

ClearSpeed CSX600 250 MHz clock 96 high-performance processing elements 576 Kbytes PE memory 128 Kbytes on-chip scratchpad memory 25,000 MIPS 50 GFLOPS single or double precision 3.2 Gbytes/s external memory bandwidth 96 Gbytes/s internal memory bandwidth 2 x 4 Gbytes/s chip-to-chip bandwidth Courtesy of CSX600 Overview on http://www.clearspeed.com/ 11/14/2018 cpeg323\Topic1a.ppt

C-64 Chip Architecture On-chip bisection BW = 0.38 TB/s, total BW to 6 neighbours = 48GB/sec 11/14/2018 cpeg323\Topic1a.ppt