Defect and High Level Fault Modeling in Digital Systems REASON Session, MINSK November 10, 2004 Defect and High Level Fault Modeling in Digital Systems R. Ubar Tallinn Technical University D&T Laboratory Estonia

Introduction to Digital Test Outline Introduction to Digital Test Defect oriented testing High-level fault modelling Decision Diagrams Comparison of fault models Experimental data Conclusions

Introduction: the Problem is Money? Cost of quality How to succeed? Try too hard! How to fail? (From American Wisdom) Cost Cost of testing 100% Test coverage function Cost of the fault Time Conclusion: “The problem of testing can only be contained not solved” T.Williams Quality Optimum test / quality 0% 100%

Two Approaches to Testing Testing of functions: 1 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 50% 75% 3. pattern 4. pat. 87,5% 93,75% 100% 2 Combinational circuit under test n Truth table: Patterns Functions 1 00…000 00…001 00…010 … 11…111 2n-1 01 01 01…101 00 11 00…011 00 00 11…111 … 00 00 00…111 2 Number of patterns tested 50%! 2n 2n Number of functions 1 2

Two Approaches to Testing Testing of functions: Testing of faults: 4. pat. Not tested faults Faults covered by 1. pattern 2. pattern 3. patttern 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 50% 75% 3. pattern 4. pat. 87,5% 93,75% 100% 100% Testing of faults Testing of functions 100% will be reached when all faults from the fault list are covered 100% will be reached only after 2n test patterns

Defect oriented testing Outline Introduction Defect oriented testing High-level fault modelling Modelling defects with Decision Diagrams Comparison of high-level fault models Experimental data Conclusions

Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

Mapping Transistor Faults to Logic Level A transistor fault causes a change in a logic function not representable by SAF model Function: y Faulty function: x1 x4 Short 0 – defect d is missing 1 – defect d is present d = Defect variable: x2 Generic function with defect: x3 x5 Mapping the physical defect onto the logic level by solving the equation:

Mapping Transistor Faults to Logic Level Function: Faulty function: Generic function with defect: y x1 x4 Short Test calculation by Boolean derivative: x2 x3 x5

Functional Fault vs. Stuck-at Fault Full 100% Stuck-at-Fault-Test is not able to detect the short:  No Full SAF-Test Test for the defect x1 x2 x3 x4 x5 1 - 2 3 4 5 Functional fault The full SAF test is not covering any of the patterns able to detect the given transistor defect

Defect coverage for 100% Stuck-at Test Results: the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

Generalization: Functional Fault Model Constraints calculation: Fault-free Faulty d = 1, if the defect is present Component with defect: Constraints: Component F(x1,x2,…,xn) y Wd Defect Fault model: (dy,Wd), (dy,{Wkd}) Logical constraints

Fault Table: Mapping Defects to Faults

Functional Fault Model for Stuck-ON x1 x2 y yd 1 Z: VY NOR gate Stuck-on VDD x1 x2 RN Y x1 x2 RP VSS Condition of the fault potential detecting: Conducting path for “10”

Functional Fault Model for Stuck-Open NOR gate Test sequence is needed: 00,10 x1 x2 y yd 1 Y’ Stuck-off (open) t x1 x2 y 1 0 0 1 2 1 0 1 VDD x1 x2 Y x1 x2 VSS No conducting path from VDD to VSS for “10”

Functional Fault Model xk x*k Example: Bridging fault between leads xk and xl The condition means that in order to detect the short between leads xk and xl on the lead xk we have to assign to xk the value 1 and to xl the value 0. d xl xk*= f(xk,xl,d) Wired-AND model

Functional Fault Model Example: Bridging fault causes a feedback loop: A short between leads xk and xl changes the combinational circuit into sequential one x1 & y x2 & x3 Equivalent faulty circuit: x1 & y & x2 t x1 x2 x3 y 1 0 1 0 2 1 1 1 1 x3 Sequential constraints: &

High-level fault modelling Outline Introduction Defect oriented testing High-level fault modelling Modelling defects with Decision Diagrams Comparison of high-level fault models Experimental data Conclusions

Register Level Fault Models RTL statement: K: (If T,C) RD  F(RS1, RS2, … RSm),  N Components (variables) of the statement: RT level faults: K  K’ - label faults T  T’ - timing faults C  C’ - logical condition faults RD  RD - register decoding faults RS  RS - data storage faults F  F’ - operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults K - label T - timing condition C - logical condition RD - destination register RS - source register F - operation (microoperation)  - data transfer  N - jump to the next statement

Microprocessor Fault Model Faults affecting the operation of microprocessor can be divided into the following classes: ·        addressing faults affecting register decoding; ·        addressing faults affecting the instruction decoding and -sequencing functions; ·        faults in the data-storage function; ·        faults in the data-transfer function; ·        faults in the data-manipulation function.

Fault Models and Tests Dedicated functional fault model for multiplexer: stuck-at-0 (1) on inputs, another input (instead of, additional) value, followed by its complement value, followed by its complement on a line whose address differs in one bit Functional fault model Test description

Fault modelling with Decision Diagrams Outline Introduction Defect oriented testing High-level fault modelling Fault modelling with Decision Diagrams Comparison of high-level fault models Experimental data Conclusions

Binary Decision Diagrams 1 x1 Functional BDD 1 x2 x3 Simulation: x4 x5 0 1 1 0 1 0 0 Boolean derivative: x6 x7

High-Level Decision Diagrams Superposition of High-Level DDs: A single DD for a subcircuit 2 y # 4 1 R 2 M1 2 y y 3 1 R + R 1 2 R2 1 IN + R 2 1 IN 2 R 1 3 y 2 R * R R2 + M3 1 2 1 IN* R 2 M2 Instead of simulating all the components in the circuit, only a single path in the DD should be traced

Fault Model for Decision Diagrams Each path in a DD describes the behavior of the system in a specific mode of operation The faults having effect on the behaviour can be associated with nodes along the path A fault causes incorrect leaving the path activated by a test

Fault Model for Decision Diagrams D1:  the output edge for x(m) = i of a node m is always activated D2:         the output edge for x(m) = i of a node m is broken D3:   instead of the given edge, another edge or a set of edges is activated

Test Generation for Microprocessors High-Level DDs for a microprocessor (example): Instruction set: DD-model of the microprocessor: 1,6 A I IN I1: MVI A,D A  IN I2: MOV R,A R  A I3: MOV M,R OUT  R I4: MOV M,A OUT  A I5: MOV R,M R  IN I6: MOV A,M A  IN I7: ADD R A  A + R I8: ORA R A  A  R I9: ANA R A  A  R I10: CMA A,D A   A 3 2,3,4,5 OUT I R A 4 7 A + R A 8 2 A  R R I A 9 5 A  R IN 10  A 1,3,4,6-10 R

Microprocessor Fault Model For multiplexers under a fault, for a given source address any of the following may happen: F1:  no source is selected F2:  wrong source is selected; F3: more than one source is selected and the multiplexer output is either a wired-AND or a wired-OR function of the sources, depending on the technology. 1,6 A I IN 2,3,4,5 A 7 A + R F1 8 A  R F2 9 A  R F3 10  A

Microprocessor Fault Model 1,6 For demultiplexers under a fault, for a given destination address: F4:  no destination is selected F5:  instead of, or in addition to the selected correct destination, one or more other destinations are selected A I IN 3 2,3,4,5 OUT I R A 4 7 F4 A + R A F5 8 2 A  R R I A 9 5 A  R IN 10  A 1,3,4,6-10 R

Microprocessor Fault Model Addressing faults affecting the execution of an instruction may cause the following fault effects: F6: one or more microorders not activated by the microinstructions of I F7: microorders are erroneously activated by the microinstructions of I F8:  a different set of microinstructions is activated instead of, or in addition to, the microinstructions of I 1,6 A I IN 2,3,4,5 A 7 A + R F6 8 A  R F7 9 A  R F8 10  A

Microprocessor Fault Model The data storage faults: F9:  one or more cells stuck at 0 or 1; F10: one or more cells fail to make a 01 or 10 transitions; F11: two or more pairs of cells are coupled; For buses under a fault: F12: one or more lines stuck at 0 or 1; F13: one or more lines form a wired-OR or wired-AND function due to shorts or spurious coupling 1,6 A I IN 2,3,4,5 A 7 A + R 8 A  R 9 A  R 10  A

Register Transfer Level Faults RTL statement: K: (If T,C) RD  F(RS1, RS2, … RSm),  N RTL faults: F14:     label faults (K/K ’) F15:       timing faults (T/T ’) F16: logic condition faults (C/C’) F17: register decoding faults (Ri/Ri’) F18: function decoding faults (f/f ’) F19: control faults ( N/ N’) F20: data storage faults ((Ri)/(Ri)’) F21: data transfer faults (/’) F22: data manipulation (function execution) faults ((f)/(f)’

Fault Modeling on High Level DDs High-level DDs (RT-level): Terminal nodes represent: RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes represent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults

Hierarchical Test Generation on DDs Hierarhical test generation with DDs: Scanning test (defect-oriented) Single path activation in a single DD Data function R1* R2 is tested Decision Diagram y 4 3 1 R + 2 IN * IN* # Data path R 2 M 3 e + 1 a * b · IN c d y 4 Test program: Control: y1 y2 y3 y4 = x032 Data: For all specified pairs of (R1, R2) Low level test data (constraints W)

Test Generation on High Level DDs High-level test generation with DDs: Conformity test (High-level faults) Decision Diagram Multiple paths activation in a single DD Control function y3 is tested R 2 y # 4 Data path 1 R R 2 M 3 e + 1 a * b · IN c d y 4 2 2 y y 3 1 R + R 1 2 1 IN + R 2 1 IN 2 R 1 3 y 2 R * R 1 2 1 Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2 Data: Solution of R1+ R2  IN  R1  R1* R2 IN* R Test program: 2 Activating high-level faults:

Comparison of high-level fault models Outline Introduction Defect oriented testing High-level fault modelling Fault modelling with Decision Diagrams Comparison of high-level fault models Experimental data Conclusions

Fault Model for Decision Diagrams D1:  the output edge for x(m) = i of a node m is always activated; notation: x(m)/i; (like logic level stuck-at faults x/0 and x/1 for the line x); D2:         the output edge for x(m) = i of a node m is broken; notation: x(m)/*; D3:   instead of the given edge for x(m) = i of a node m, another edge for x(m) = j, or a set of edges { j } is activated; notation: x(m)/ i,{ j }.

Comparison of High-Level Fault Models

Experimentral Results circuit High - level fault Hierarchical model approach (FUs+ MUX) (FUs only) F.C., % F.C., % gcd 89.9 83.0 sosq 80.0 78.5 mult8x8 74.2 69.4 ellipf 95.04 86.7 risc 96.5 83.9 diffeq 96.52 96.44 average 88.7 83.0

Conclusions Different fault models for different representation levels of digital systems can be replaced on DDs by the uniform node fault model It allows to represent groups of structural faults through groups of functional faults As the result, the complexity of fault representation can be reduced, and the simulation speed can be raised The fault model on DDs can be regarded as a generalization of the classical gate-level stuck-at fault model, and of the known higher level fault models