A Floating-Gate Technology for Digital CMOS Processes

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Presentation transcript:

A Floating-Gate Technology for Digital CMOS Processes V1 Cf Creates a DC Measurement of classic C-V curves C2 V2 C3 Vout V3 Vref V4 C4 Gain = DVout/ DVin = - C1 / Cf Brought to you by Brad and Paul

Types of Integrated Capacitors Double-Poly Capacitors Well-Based MOS Capacitors n-well + V - Thin oxide n-well + V - Thin oxide

MOS Cap: CV Measurements 5 4.5 4 3.5 3 2.5 Vref = 3.5V Output voltage (V) 2 1.5 Vref = 3.0V 1 Vref = 2.5V 0.5 -1.5 -1 -0.5 0.5 1 Input voltage - Vref (V)

MOS Cap: CV Measurements 4 Accumulation 3.5 3 Depletion 2.5 Capacitance (pF) 2 1.5 1 0.5 -1.5 -1 -0.5 0.5 1 Gate-to-well voltage (V)

MOS Capacitor FG Amplifiers 5 Region 1 Vin Vfg Vdd Vout Vt 4.5 4 Region 2 3.5 Output voltage (V) 3 2.5 Region where both capacitors are acting as linear elements 2 1.5 1.5 2 2.5 3 3.5 4 4.5 5 Input voltage (V)

MOS Capacitor FG Transistor 10-5 Vdd 10-6 Vfg Vin 10-7 10-8 Channel Current (A) Iout Sweep using two inputs: 39.6mV/e-fold 10-9 Vdd 10-10 Sweep using one input: 79.2mV/e-fold Vfg Vin 10-11 Vref Iout 10-12 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Gate voltage (V)