© CHAROTAR INSTITUTE OF TECHNOLOGY, CHANGA CHAROTAR INSTITUTE OF TECHNOLOGY OPERATING SYSTEM Input Output Management © CHAROTAR INSTITUTE OF TECHNOLOGY, CHANGA

©Copyrights Charotar Institute of Technology, Changa Topics for discussion Principles of Hardware Principles of Software I/O Software Layers Disk Management Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa One of the main function of OS is to control all the computer’s Input Output devices It should provide interface between devices and rest of the system It should also provide Device Independence Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Principles of I/O hardware People look at hardware in different ways EE people look at hardware in terms of: Chips, wires, power suppliers, motors, etc. i.e. physical components that make up it Programmers look at the interface Commands, functions, and errors reported back As a programmers, we will be concerned with how it functions and not its hardware structure Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Principles Of I/O Hardware Types of I/O Devices Device Controllers I/O Approaches Direct memory Access Interrupts Revisited Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa I/O Devices Two Types Block Devices One which stores information in fixed size blocks one with its own address Common block size range from 512 bytes to 32768 bytes Special property is that all blocks can be read or written independent of each other e.g hard disk Storage purpose Character devices Delivers of accepts a stream of characters(characte by character) without any regard to block structure Not addressable and does not have any seek operation E.g Mouse, Printer, network interface, keyboard etc Communication purpose Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Device Controllers I/O devices have components: mechanical component The mechanical component is device itself electronic component The electronic component is the device controller (adapter) Generally in form of a printed circuit card may be able to handle multiple devices. Any device connected to the computer is connected by a plug and socket, and the socket is connected to a device controller Controller has a connector through which device can be connected Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

How Device Controller works? A device controller is a part of a computer system that makes sense of the signals going to, and coming from the CPU processor Device controllers use binary and digital codes. Device Controller play an important role in order to operate that device. It's just like a bridge between device and operating system. Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Device Controllers Exchange data with CPU via registers By writing into these registers OS can command the device to deliver or accept data, to switch the device on or off By reading from the registers OS can learn the status of the device Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa The Device Controller receives the data from a connected device and stores it temporarily in some special purpose registers (i.e. local buffer) inside the controller. Then it communicates the data with a Device Driver . For each device controller there is an equivalent device driver which is the standard interface through which the device controller communicates with the Operating Systems. Thus we can say that operating system communicates with device controller through device driver A device controller (hardware) understands "software" input. It translates software input into something a hardware device understands . Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Device Controllers In addition, controllers often have buffers Which the OS can read or write Example: a video controller may have Video RAM, which is a data buffer programs or OS can write or read Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Device Controllers Monitor Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Device Controllers major tasks Controller's tasks convert serial bit stream to block of bytes perform error correction as necessary make available to main memory Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa I/O Approaches 3 ways for CPU to communicates with the control registers and its device buffers Dedicated I/O Memory-mapped I/O Hybrid Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Dedicated I/O Each control register assigned an IO port i.e. an 8 or 16 bit integer IO port and memory spaces are separate OS uses special instructions to read/write IN REG, PORT for reading from the device Read value of device’s port to CPU register (From port to cpu reg) OUT PORT, REG for writing to the device Write contents of CPU register to device’s port(Control register) (from cpu reg to port) Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Dedicated I/O Computers use dedicated I/O include most early computers, such as mainframes (IBM 360/370) Problems with this approach? Controls are at low-level No high level languages has IN/OUT operations Protections can be problematic Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Memory-Mapped I/O Each control register is assigned a unique memory address Input/output done by reading/writing to the designated memory addresses Just like a ordinary memory access Introduced in PDP-11 computer No of instructions get reduced e,.g LOOP: TEST PORT_4 //CHECK IF PORT 4 IS O :BEQ READY//IF IT IS 0 GO TO READY :BRANCH LOOP//OTERWISE CONTIUNE TESTING READY: Here Test instruction can test port just like any other memory In absence of above scheme two instructions would be needed, one to read control reg into CPU reg and then test Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Hybrid Approach Memory-mapped data buffer Dedicated I/O ports For example, Pentium use Memory address 640K to 1M for device data buffers 0 to 64K for I/O ports Why we need the internal data buffer in the devices? (checksum & buffering) Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

How Hybrid Approach works? Whenever CPU wants to read a word from memory or I/O port it puts address on bus address lines and then asserts a READ signal on bus control line A second signal is used to tell whether I/O space or memory space is needed. If it is memory space, memory responds,if I/O space then I/O responds Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa I/O approach Dedicated IO memory-mapped IO Hybrid IO Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Memory-Mapped I/O Problems for memory-mapped I/O? Cache cause problems Solution: Equip hardware to disable caching on per page basis For single-bus system, both memory and device have to examine addresses on the bus Solution: Have multiple bus For system with multiple memory buses: Devices may not see the addresses on the bus Solution: Many ways to solve the multiple buses issue Fail and try: If memory fails to respond, try other buses Snooping: A snooping device on the bus passes to devices Address filtering Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Memory-Mapped I/O Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Address Filtering in Pentium Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Ho address filtering in Pentium is done? Filter address in PCI bridge chip This chip contains range registers that are preloaded at boot time For example 64K to 1M could be marked as non memory range. Addresses that fall in this range are forwarded tp PCI bus instead of memory Disadvantage: Figuring at boot time Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Direct Memory Access Memory-mapped or not, CPU needs to address controllers to exchange data request data one byte at a time How it works? Suppose I want to read data from HD to print it. Its controller first brings block from device to its internal buffer. Then do error correction Then gives interrupt to CPU Then OS reads it from buffer to main memory Or request data in bulk This is accomplished via DMA Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Direct Memory Access Can use only if there is DMA controller DMA controller can be built in device controller, which requires one DMA controller for each device More commonly, a single DMA controller on the mainboard for regulating transfer to multiple devices Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Direct Memory Access Address Reg, a byte counter reg and Control Reg: Specifies the I/O port,direction of transfer(that is reading from I/O or writing to I/O),the tranfer unit(byte at a time or word at a time) Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Direct Memory Access DMA controller vary in sophistication Simplest one handles 1 transfer at a time Complex one have multiple channels With each channel deals with one device Multiple sets of registers sneak in occasional burst Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Issues with DMA How to access the bus? Cycle stealing or burst mode Where to store the data? Directly into memory (fly by mode) or in DMA buffer How to address the memory? Virtual or physical address? Either directly keep physical address on DMA register or keep MMU to to translate logical to physical address Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa How to access bus Buses operate in two modes: word at a time mode and block mode In word mode, DMA controller requests for transfer of one word and gets it. If CPU also wants the bus it has to wait. The mechanism is called cycle stealing because the device controller sneaks in and steals an occasional bus cycle from CPU delaying it slightly In block mode, DMA controller tells device to acquire bus, issue a series of transfer then release the bus. This form of operation is called burst mode More efficient as acquiring bus takes time and multiple words transferred in one bus acquisition Disadvantage: Can block CPU if burst is long Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Pros and Cons of DMA Pros: free up CPU Use CPU instead of DMA if: Device speed is fast CPU has nothing else to do want to Save money (by getting rid of DMA) Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Interrupts Revisited How interrupts happens Classified e-Material ©Copyrights Charotar Institute of Technology, Changa 32 32

©Copyrights Charotar Institute of Technology, Changa How it works? When device completes its task it send a signal to interrupt controller via bus If interrupt controller is free then interrupt is services otherwise not How to service interrupt? The interrupt controller sends a signal to CPU The number on address lines is used as an index into a table called interrupt vector to fetch a new program counter This PC points to interrupt service procedure which is then services After service, CPU gives ack to Interrupt controller Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Precise and Imprecise Interrupts (1) Properties of a precise interrupt PC (Program Counter) is saved in a known place. All instructions before the one pointed to by the PC have fully executed. No instruction beyond the one pointed to by the PC has been executed. Execution state of the instruction pointed to by the PC is known. Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Precise and Imprecise Interrupts (2) An interrupt that is not precise is called an Imprecise Interrupt This interrupts make operating systems slow Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Principles of I/O Software Goals of I/O Software Programmed I/O Interrupt-driven I/O I/O using DMA Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Goals of I/O Software(1) Device independence: Program should access all I/O devices in the same or similar ways Without specify the device in advance Example: when reading a file, do not care if The file is in floppy, disk, or CD-ROM Uniform naming The name of a file or device should be a string or an integer not depending on which device Error handling handle as close to the hardware as possible Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

Goals of I/O Software(2) Synchronous vs. asynchronous transfers blocked vs. interrupt-driven Buffering data coming off a device cannot be stored in final destination right away Sharable vs. dedicated devices Some devices such as Disks are sharable, but some others are not sharable Make dedicated devices appear sharable Printer can be made sharable Tape drives would not be sharable Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Programmed I/O Three different ways to perform I/O Programmer I/O is the simplest Interrupt-driven is the most common DMA I/O used to improve efficiency Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Programmed I/O CPU wait for the I/O to complete This is called Polling or Busy waiting Very bad But simple to program Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Programmed I/O Copy_from_user (buffer, p, count); /*p is kernel buffer */ For (i=0;i<count;i++) { /*loop on every character*/ while(*printer_status_reg!=READY); /*loop until ready*/ *printer_data_register=p[i]; /*output one character*/ } Return_to_user(); Writing a string to printer using programmed I/O Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Programmed I/O Writing a string to printer using programmed I/O Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Interrupt-Driven I/O CPU setups and start I/O operation CPU goes off to do other things When I/O is done, CPU is interrupted CPU handles the interrupt CPU resumes interrupted operation Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Interrupt-Driven I/O Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Interrupt-Driven I/O Copy_from_user(buffer,p,count) Enable_interrupts(); while(*printer_status_reg!=READY); *printer_data_register=p[0]; Scheduler(); Code executed when print system call is made Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa Interrupt-Driven I/O If(count==0) { unblock_user(); } else { i=i+1; *printer_data_register=p[i]; count-count-1; } acknowledge interrupt(); return_from_intertupt(); Interrupt service procedure Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa I/O Using DMA An obvious con for interrupt-driven I/O is the frequent interrupts The solution is to use DMA Idea is to let DMA controller handle the I/O one character at a time In other words, busy wait with DMA Classified e-Material ©Copyrights Charotar Institute of Technology, Changa

©Copyrights Charotar Institute of Technology, Changa I/O Using DMA Copy_from_user(buffer,p,count); acknowledge_interrupt(); Set_up_DMA_controller(); unblock_user(); Scheduler(); return_from_interrupt); (a) (b) Printing a string using DMA (a) Code executed when the print syscall is made (b) Interrupt service procedure Home Classified e-Material ©Copyrights Charotar Institute of Technology, Changa