EMC problems of DSOI device and circuits Binhong LI@IMECAS IHEP mini workshop 20160714

Topics All about DSOI： Compensation of TID； Dynamically adjustable circuit by VSOI2; EMC problems of the circuits; libinhong@ime.ac.cn

TID Compensation NMOS transistor TID experiment NMOS was biased under OFF state: VS=VG=0V, VD=1.8V, Vsub=0V Radiated with Co60 gamma rays with 50 Rad (Si) /s Quick review of TID compensation by applying a negative bias on VSOI2 libinhong@ime.ac.cn

TID Compensation NMOS transistor TID experiment libinhong@ime.ac.cn Quick review of TID compensation by applying a negative bias on VSOI2 libinhong@ime.ac.cn

TID Compensation NMOS transistor TID experiment IV curve shifts negatively due to radiation induced holes accumulated in oxide. Since buried oxide are thicker than gate oxide, the main source of holes accumulation is in buried oxide. By applying a negative voltage, the leakage current and threshold voltage can be recovered to pre-irradiation level. For our case of study after 2M rad (Si), -7V on middle silicon layer is enough to compensate. Quick review of TID compensation by applying a negative bias on VSOI2 libinhong@ime.ac.cn

Dynamically adjustable circuit Ring oscillator frequency adjustment We use a 101 stages ring oscillator to test VSOI2 impact on circuit performance. adjust Vthn and Vthp separately threshold voltage (Vth) controlled by the back gate. Since Vth can be controlled by the back gate, with middle silicon layer, we can adjust Vthn and Vthp separately libinhong@ime.ac.cn

Dynamically adjustable circuit Ring oscillator frequency adjustment We use a 101 stages ring oscillator to test VSOI2 impact on circuit performance. τd is related to Vth, Vdd, and also Vsoi2 With Vsoi2 increasing, Vthn and Vthp will decrease. So by changing Vsoi2, we can adjust RO’s frequency and power consumption libinhong@ime.ac.cn

Dynamically adjustable circuit Ring oscillator frequency adjustment Best performance and highest power consumption: Vthn =+5V, Vthp =-5V libinhong@ime.ac.cn

Summary By introducing middle silicon layer: Compensation of TID with negative bias; Adjustment of circuit performance and power consumption; libinhong@ime.ac.cn

EMC of Circuit Electromagnetic compatibility of integrated circuit The increases of complexity and integration make EMC concern moving from system level to IC level. libinhong@ime.ac.cn

EMC of DSOI circuit Conducted immunity (150kHz – 1GHz)： According to [IEC62132-4], we inject a sinusoidal wave with different frequency and amplitude. The RF disturbance is superimposed on the useful signal to simulate the noise injection in the real world . libinhong@ime.ac.cn

EMC of DSOI circuit DSOI Ring oscillator We limit the maximum noise power at 30dBm. The frequency of noise varied from 1MHz to 1GHz. The failure criteria contains a static margin (±10% of power supply) and a dynamic margin( ± 10% of output signal period),

EMC of DSOI circuit DSOI Ring oscillator libinhong@ime.ac.cn

EMC of DSOI circuit DSOI Ring oscillator Electromagnetic Immunity (EMI)： VSOI2 and Substrate are vulnerable libinhong@ime.ac.cn

EMC of DSOI circuit Compare FDSOI and DSOI, VDD’s EMI are same DSOI Ring oscillator Compare FDSOI and DSOI, VDD’s EMI are same libinhong@ime.ac.cn

EMC of DSOI circuit Compare FDSOI and DSOI, substrate’s EMI: DSOI Ring oscillator Compare FDSOI and DSOI, substrate’s EMI: When Vsoi2=0V DSOI circuits has better EMI than FDSOI, due to SOI2 shielding. But when Vsoi2=-5V, the EMI level is worse than FDSOI libinhong@ime.ac.cn

EMC of DSOI circuit Problems: From previous study, that coupling capacitance between SOI1 and substrate are decrease: CFD>CDSOI(VSOI2=0V)>CDSOI(VSOI2=-1V); ?We test the impedance Network with VNA of device that we cant find different of capacitance for different VSOI2; More detail research in capacitance characterization are in progress; We propose that the EMI changing are due to circuit performance changing with back gate voltage. libinhong@ime.ac.cn

Summary Middle silicon layer works as an input, need to be characterized EMI performance, and useful EMC design rule need to be evaluated. Negative bias on Vsoi2 has impact on capacitance between SOI1 and substrate, which need to be checked; Back gate effect to circuit performance and EMI level need to be studied in detail. libinhong@ime.ac.cn

Thanks libinhong@ime.ac.cn