Topics 16 x 16 multiplier example.

The FPGA design process Translation from HDL. (synthesis, translation) Logic synthesis. (mapping) Placement and routing. (place and route) Configuration generation. (program file generation)

Design experiments Synthesize with no constraints. Synthesize with timing constraint. Tighten timing constraint. Synthesize with placement constraints.

Post-translation simulation model HDL model in terms of FPGA primitives. Example: X_LUT4 \p12_Madd__n0015_Mxor_Result_Xo<1>1 ( .ADR0(x_7_IBUF), .ADR1(y_13_IBUF), .ADR2(c12[7]), .ADR3(row12[8]), .O(row13[7]) );

Mapping report Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 501 out of 1,024 48% Logic Distribution: Number of occupied Slices: 255 out of 512 49% Number of Slices containing only related logic: 255 out of 255 100% Number of Slices containing unrelated logic: 0 out of 255 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 501 out of 1,024 48% Number of bonded IOBs: 64 out of 92 69% Total equivalent gate count for design: 3,006 Additional JTAG gate count for IOBs: 3,072 Peak Memory Usage: 64 MB

Static timing analysis report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns. --------------------------------------------------------------------------------

Static timing report: delays along paths Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Pad to Pad ------------------+----------------------+-----------+ Source Pad |Destination Pad| Delay | x<0> |p<0> | 5.824| x<0> |p<10> | 10.675| x<0> |p<11> | 11.214| x<0> |p<12> | 11.753|

Routing report Phase 1: 1975 unrouted; REAL time: 11 secs The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

Static timing after routing Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 38.424ns. --------------------------------------------------------------------------------

Timing constraint Use timing constraint editor:

Post-map static timing report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns.

Post-routing static timing report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 31.984ns.

Tighter timing constraints Tighten requirement to 25 ns. Post-place-route timing report: Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 25 nS ; 20135312 items analyzed, 11 timing errors detected. (11 setup errors, 0 hold errors) Maximum delay is 31.128ns.

Report on a violated path Slack: -6.128ns (requirement - data path) Source: y<0> (PAD) Destination: p<30> (PAD) Requirement: 25.000ns Data Path Delay: 31.128ns (Levels of Logic = 31) Data Path: y<0> to p<30> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K5.I Tiopi 0.825 y<0> y<0> y_0_IBUF SLICE_X2Y11.G4 net (fanout=31) 1.792 y_0_IBUF SLICE_X2Y11.Y Tilo 0.439 c2<5> p0_Madd__n0017_Mxor_Result_Xo<1>1 SLICE_X2Y11.F4 net (fanout=2) 0.304 row1<6> SLICE_X2Y11.X Tilo 0.439 c2<5> p1_Madd__n0019_Cout1 SLICE_X5Y16.F3 net (fanout=2) 0.784 c2<5> SLICE_X5Y16.X Tilo 0.439 c3<5> p2_Madd__n0019_Cout1 SLICE_X2Y18.G4 net (fanout=2) 0.668 c3<5> SLICE_X2Y18.Y Tilo 0.439 row5<4> p3_Madd__n0019_Mxor_Result_Xo<1>1

Power report Power summary: I(mA) P(mW) ---------------------------------------------------------------- Total estimated power consumption: 333 --- Vccint 1.50V: 0 0 Vccaux 3.30V: 100 330 Vcco33 3.30V: 1 3 Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 0 0 Signals: 0 0 Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3 Thermal summary: Estimated junction temperature: 36C Ambient temp: 25C Case temp: 35C Theta J-A: 34C/W

Power report: decoupling capacitance Decoupling Network Summary: Cap Range (uF) # ---------------------------------------------------------------- Capacitor Recommendations: Total for Vccint : 4 470.0 - 1000.0 : 1 0.0100 - 0.0470 : 1 0.0010 - 0.0047 : 2 --- Total for Vccaux : 4 Total for Vcco33 : 10 0.470 - 2.200 : 1 0.0470 - 0.2200 : 2 0.0100 - 0.0470 : 3 0.0010 - 0.0047 : 3

Improving area Floorplanner window: Chip floorplan LEs

Rat’s nest wiring

Routing editor view

Adding placement constraints Must add attributes to the Verilog: // synthesis attribute rloc of p0 is X0Y0 multrow p0(row0,x,y[1],y[0],c0,row1,c1);

Editing constraints Use constraints editor to place constraints:

Design browser pane

Drag and drop constraints

Change the shape of constraints

Full set of placement constraints

Placement results

New timing report After placement constraints: 19742142 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 29.934ns. Compares to 31 ns for unconstrained placement.

Detailed routing constraints