COOLRUNNER II REAL DIGITAL CPLD Ravi Kumar Vommina CPE 695 11/15/2018 UAH

Contents Introduction Features Architecture Advanced Features Applications ISE 6.1 Cool Runner II Family parameters 11/15/2018 UAH

Introduction Reconfigurable Computing Platforms Implementing algorithms directly in hardware Parallelism nature of Hardware Efficient Implementation FPGA (Field Programmable gate Array) Configurable logic blocks and routing resources CLB uses LUTs to implement Boolean functions Inclusion of hard cores CPLD (Complex programmable logic device) PLA , programmable AND plane,fixed OR plane PAL, both AND and OR planes 11/15/2018 UAH

Common logic may be shared in Cool Runner II Introduction PAL: Requires 4 pt’s! PLA: Requires only 3 pt’s! A B C A B C Can NOT share common logic X = A & B # C Y = A & B # !C X Y X Y Indicates ‘used’ junction Common logic may be shared in Cool Runner II Indicates ‘unused’ junction Indicates ‘fixed’ junction 11/15/2018 UAH

Cool Runner II Features Real Digital patented design technology enabling high performance and ultra low power consumption. true CMOS both in process technology and design technique 1.8 V system, fastest low power CPLD using real digital technology 0.18u process technology CMOS CPLD Static Icc of less than 100 micro amps at all times 100% CMOS product term generation 11/15/2018 UAH

CMOS V DD In steady state there exist always a finite resistance path between Vout and either VDD or Ground. Ideal static power should be zero Small static power consumption exists due to leakage currents and sub threshold conduction that is < 100 micro amps Total power = dynamic+short circuit +static Short circuit current flow is due to the delay in rise and fall times of input. Dynamic power = C .VDD2/ 2 . f CMOS inverter V V in out C L V V DD DD R p V V out out R n 11/15/2018 UAH V in 5 V V DD in 5

Product term generation B C D Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Design for speed: Alternative structures CL A C3 B C2 C C1 D 11/15/2018 UAH

100% CMOS Product Generation Delay < 0.1ns Delay < 0.3ns 11/15/2018 UAH

Cool Runner Architecture – High Level View 11/15/2018 UAH

Cool Runner II Macro cell view 11/15/2018 UAH

Global Clock Signals Clock input is buffered that drives multiple internal global signal traces to deliver low skew and reduce loading delays 11/15/2018 UAH

Recap High level View 16 macro cells in a function block Function blocks use PLA Function blocks interconnect with advanced interconnect matrix AIM is highly connected low power rapid switch Macro cell View 56 product terms 4 control terms, 3 product terms One flipflop as (D,T or latch) , ( edge or dual edge triggered) Xilinx software makes the choice when to choose product or global or control term 11/15/2018 UAH

Cool Runner-II I/O Characteristics Programmable Output capabilities performed with software attributes Open drain with pull up Slew rate 11/15/2018 UAH

Cool Runner II input view Schmitt Trigger Input 11/15/2018 UAH

Cool Runner II Input Characteristics Termination Options Bus- Hold (Weak Keeper) Pull-Up CGND During power up device is in Quiescent state 11/15/2018 UAH

Advanced Features – Data Gate 11/15/2018 UAH

Advanced Features – Clocking Options 11/15/2018 UAH

Advanced Features-Cool Clock 11/15/2018 UAH

Using the advanced features Clock divide declaration Instantiation Schmitt Trigger input 11/15/2018 UAH

Advanced Features-On the fly Configuration Initial pattern is loaded into a configuration shifter The pattern first transfers into nonvolatile memory The pattern is then read from NV to SRAM for actual cell operation Leaves ability to reload the NV memory as xilinx says, “On the Fly” 11/15/2018 UAH

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Impact Menu 11/15/2018 UAH

Selecting OTF 11/15/2018 UAH

Cool Runner II Features Advanced Design Security Hot Pluggable Wide package availability Supports Multi Voltage standards 11/15/2018 UAH

Applications Ideal for high speed designs: High performance CPLD Advanced features Double data rates Target device for portable designs: Lowest power Maximum battery life Lower heat dissipation Small packaging Chip scale packaging 11/15/2018 UAH

PDA Battery Compact Flash Flash SRAM LED P Docking Cradle LCD Keypad SMBus Battery Compact Flash Flash SRAM IrDA LED P UART Docking Cradle LCD SPI Keypad Touchscreen 11/15/2018 UAH

Interface for DDR SDRAM Interface Address Data Control DDR SDRAM P Double data rates Address translation 11/15/2018 UAH

ISE6.1Design Flow An active project space is created. Existing VHDL modules can be added or new ones can be created in the project. A user constraint file is specified that maps the input and out put signals to the actual pins of the device Synthesis of the design is performed by just selecting the implement design option. Device is configured by IMPACT. 11/15/2018 UAH

Cool Runner II 11/15/2018 UAH

Bibliography WWW.Xilinx.com http://bwrc.eecs.berkeley.edu/IcBook/ 11/15/2018 UAH