Physics of Semiconductor Devices (2) Institute of Microelectronics and Optoelectronics Hakro Ayaz Ali

Outlines Introduction to MOSFET Parasitic Elements Gate Overlap Capacitances MOSFET Length and Width Definitions MOSFET Circuit Models

Introduction to MOSFET Parasitic Elements In the MOSFET the Source/Drain Junction portion is a parasitic component. These junctions have a resistance and capacitances. Source/Drain PN junction capacitance Gate to source/Drain overlap capacitance

Gate Overlap Capacitances In the self aligned process, the polysilicon gate is employed as the mask to define the source and drain regions . The overlaps occur because the remaining processing steps require heating of the wafer. This gives rise to lateral diffusion of the source/drain dopants so the polysilicon gate overlaps the source and drain regions of the final structure.

(3.28)

The third overlap capacitance that can be significant due to the overlap between the gate and the bulk (CGBO) as shown in this figure. This occurs due to the overhang of the transistor gate required at one end and is a function of the effective polysilicon width that is equivalent to the drawn channel length.

For a typical 2 CMOS process the junction depth Xj=0 For a typical 2 CMOS process the junction depth Xj=0.3 and thus lov is approximately 0.21

In a MOSFET, in addition to the outer fringing field capacitance, there is another parasitic capacitance which must be taken into account while calculating the overlap capacitance.

MOSFET Length and Width Definitions At the device level, the circuit designer has control over only two parameters, the device channel length L and width W, that have important effects on device performance. For increased current drive and hence circuit speed a large W and small L is required. It is important to understand what device L and W stand for from the modeling point of view.

Effective or Electrical Channel Length The channel length L as the distance between the source-drain junction The difference between the drawn and final gate length is Lvar = (Lm– Lpoly) During the high temperature fabrication steps the source and drain junctions not only diffuse vertically but also move laterally under the gate. This lateral diffusion Ldi, is typically 0.6-0.8 of the source-drain junction depth Xj, depending upon the type of dopants. L = Lm – Lvar - 2Ldif (Effective channel Length)

Effective or Electrical Channel width In MOSFET isoplanar processes different devices are isolated from the neighboring devices by the so called field oxide whose thickness tfox, >> tox. During high temperature processing steps, the heavily doped region under the field oxide will encroach into the channel, which when combined with some fabrication process, causes tapering of the thin oxide (active) to thick oxide (field) resulting in a structure that looks like a bird’s beak. This causes the effective, or electrical, device width W to be smaller than the drawn device width Wm, (physical mask dimension) by a factor ΔW (shown in Figure ) Thus W = Wm, - Δ W (effective channel width)

MOSFET Circuit Models The equivalent circuit model for the DC operation of a MOSFET The drain-source current is represented by a voltage controlled current source Ids The Ibs and Ibd are the DC source and drain pn junction currents respectively.

The Ids ,Ibs and Ibd are all nonlinear functions of the node or terminal voltages. To solve the nonlinear circuit equation, the equivalent circuit model is converted into its companion model as shown in Figure. In this figure gm, gmbs and gds are small signal MOSFET intrinsic conductances.

For transient and small-signal analysis, we need capacitance components as well as the previously described DC model. This Figure shows the complete equivalent circuit for a MOSFET. Cbs and Cbd are the source and drain junction capacitance respectively while Qbs and Qbd are the corresponding charges. The gate overlap capacitances are shown as CGSO CGDO and CGBO. The twelve intrinsic capacitances are shown as CGS, CGD, CGB, CBS, CBD, CBG, CSD, CSB, CSG, CDS, CDG, CDB. These nonlinear and nonreciprocal capacitances are required to conserve the charge in the device during the transient analysis

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