D.-H. Kim and J. A. del Alamo MIT Performance Evaluation of 50 nm In0.7Ga0.3As HEMTs For Beyond-CMOS Logic Applications D.-H. Kim and J. A. del Alamo MIT Good morning! As introduced, my name is Dae-Hyun Kim. In this presentation, I am going to present for the first time Performance evaluation of 50 nm InGaAs HEMTs for beyond-CMOS Logic Applications. Before starting this presentation, I’d like to inform you that this work has been done by collaboration between MIT and Seoul National University, and this work has been sponsored by MARCO-MSD at MIT, and TND at Seoul National University. The epi-wafers, which were used in this study, have been supplied by MBE Technology. J.-H. Lee and K.-S. Seo Seoul National University Sponsors: MARCO-MSD, TND Acknowledgement: MBE Technology IEDM December 14, 2005

Contents Introduction Fabrication of InGaAs HEMTs Characterization of InGaAs HEMTs Logic Parameters Scaling Limit Benchmarking against Si MOSFETs Conclusions This is the outline of my presentation. I will begin with a brief introduction, and then I will discuss in detail the fabrication and characterization of InGaAs HEMTs. Especially, I will focus on Logic relevant parameters, such as gate-delay, subthreshold slope and Ion/Ioff ratio, and l will also investigate the scaling limit of InGaAs HEMTs. Before concluding this presentation, I will benchmark this technology against the advanced Si MOSFETs, in order to explore the logic suitability of InGaAs HEMT.

InGaAs HEMTs: beyond-the-roadmap logic technology? The Moore’s law has been the guiding principle for the semiconductor industry for over 30 years. Sustaining Moore’s law requires transistor scaling, as shown in this figure. The physical gate length of Si transistors, which is used in current 65 nm node, is about 30 nm. And it is expected that the size will reach about 10 nm in 2011, which could be the ultimate limit for CMOS scaling. Therefore, identifying a new logic device technology is becoming increasingly pressing. Candidates, which are often mentioned, are carbon nanotubes, semiconductor nanowires and further out, spintronics. However, many of these device concepts are hardly beyond the prototyping stage. In contrast, III-V FETs and in particular InAlAs/InGaAs High Electron Mobility Transistors, so called HEMTs, constitute a very real device technology, which is worth considering in this study. Acknowledgement : Robert Chau, Intel

InGaAs HEMTs for the past 20 years Tremendous intrinsic potential of InGaAs HEMT technology Ultra High-speed ICs based on InGaAs HEMT Technology 100 Gb/s MUX, NTT (IEDM-02) 160~215 GHz (20 dB), TRW (IRPM-02) 180~205 GHz (14 dB), HRL (MGWL-01) This shows the highest cutoff frequency data for each semiconductor technology, as a function of the reported year. As you can see right here, III-V InGaAs HEMT is the fastest semiconductor technology in existence, and the most important thing is that it is very realistic device technology, compared to other candidates. For the past almost 20 years, InGaAs HEMT technology has held the world record of frequency response, as measured by fT, which is a current record of 562 GHz by Fujitsu. As a result from this tremendous intrinsic potential, several ultra high speed integrated circuits have also been demonstrated, based on this technology, such as 100 Gb/s MUX and above 200 GHz MMIC. Unfortunately, however, at the time when we started this work, there haven’t been enough and thorough studies about InGaAs HEMTs as a logic candidate. This was the motivation of our study, and I’m going to show you some results, keeping in mind this point of view. What would it take for InGaAs HEMT to become mainstream logic technology?

Epitaxial Layer Structure n+ Cap InGaAs, x = 0.53 20 nm Stopper InP 6 nm Barrier InAlAs, x = 0.52 8 nm δ-doping Si - Spacer 3 nm Channel InGaAs, x = 0.7 4 nm Buffer 500 nm 3 Inch S. I. InP Substrate This shows the epitaxial layer structure, which was used in this study. The epi-wafer was grown by MBE. We employed strain InGaAs channel with 70 % indium content in order to enhance carrier’s transport property, and we also used 6 nm thin InP layer which acts as a good gate recess etch-stopper as well as a good surface passivation layer. Typically achievable hall mobility was around 11,000 cm2/V-sec, at room temperature. Grown by Molecular Beam Epitaxy Strain InGaAs Channel & InP Stopper mn,hall = 11,200 cm2/V-sec

Fabrication of 50 nm InGaAs HEMTs PMMA Mesa Copolymer Ohmic ZEP-520 SiNx Lg=50 nm SiNx This shows the overall fabrication procedure of 50 nm InGaAs HEMT; which are Mesa Isolation, Alloyed Source/Drain Ohmic contact, and SiNx pre passivation. After making T-shape profile by electron beam lithography, Schottky gate was done through lift-off process. The right two SEM images show the cross-section of the gate before and after Schottky metallization, where the achievable metallagical gate length is about 50 nm. Next, let me give you more detail on the electron beam lithography process, how we could get as small as 50 nm T-gate and how we could get this shape of recess profile. EBL & Recess Schottky

EBL for 50 nm T-gate Fabrication - Conventional Method - - Newly Proposed Method - Head Exposure Foot Exposure PMMA ZEP P(MMA-MAA) ZEP Head Exposure PMMA Foot Exposure P(MMA-MAA) This shows conventional and newly proposed EBL for T-gate fabrication. Instead of using the conventional method of sequential exposure and development of gate head and gate foot, where the final shape of gate foot is very sensitive to the gate head exposure energy, in this method, we exposed and developed the gate foot, first. And then, after coating the other two layers again, head exposure and development were done. Simply by changing the exposure sequence, we were able to eliminate the effect of gate head exposure energy into the bottom resist layer during gate foot development, so that a much smaller line could be achieved in this manner. Next, let me show you a critical process step of gate-recess etching, which is immediately after this EBL step.  Minimum Lg = ~ 100 nm  Minimum Lg = 50 nm

Two-Step Recess Technology Selective Wet-Etching ZEP InP Etch-stopper Ar-Based RIE InGaAs SiNx SiNx Gate recess has been done by sequential procedures of wet and dry-etching, which was originally proposed by Dr. Suemitsu and called as two-step recess technology. After wet-etching of InGaAs cap with enough side recess spacing by Citric-acid based wet-etchant, then InP etch-stopper was an-isotropically etched by Ar-based RIE. In this SEM image, we can clearly see the etched region of InGaAs capping layer as well as InP etch-stopper, which finally forms two-step recess profile. Two-Step Recess - InGaAs Cap : Wet (Citric Acid) - InP Stopper : Dry (Ar-RIE) < Ref. : Suemitsu et al. (IEDM 1998) >

Optimization : Structure Variation InGaAs Ti InGaAs Ti InP InP tins = 17 nm B = 0.4 eV tins = 11 nm B = 0.6 eV InAlAs InAlAs InGaAs InGaAs Ti/Pt/Au on InP : Type A Ti/Pt/Au on InAlAs : Type B Buried Pt (PtAs4) InGaAs InGaAs Pt This shows the detailed device structures, which have been considered in this study. Usually, InGaAs HEMTs are modulated directly by Metal gate with Schottky depletion. As a result, it has been well known that they seriously suffered from large gate leakage current, though it basically depends on Schottky barrier height. In order to explore the logic relevant performance of InGaAs HEMTs, we have made actually four different types of devices, in this study. Key factors that we have focused on are Schottky barrier height and insulator thickness. For example, type-A device, which has Ti-Schottky on InP etch-stopper, has the lowest Schottky barrier height and the largest insulator thickness. On the contrary, Type-B is more general device structure of InGaAs HEMT, where Schottky gate is formed on InAlAs barrier layer. For the purpose of increasing the Schottky barrier height further, in the Type-C devise design, we have employed Platinum Schottky contact, which has higher metal work function than that of Ti. Generally, gate-to-channel distance begins to play more important role as scaling down. To further investigate the role of insulator thickness on the device’s logic characteristics, we have also considered type-D design, which is composed of buried Platinum Schottky contact. In general, Platium can easily react with arsenic through thermal treatment or annealing, which finally forms metalorgical compound of PtAs4. Applying this method into the Type-C, we could get the Type-D device, which has the highest Schottky barrier height and the smallest insulator thickness, at the same time. As explained now, it is clear that the direction from type-A via B and C to type-D is exactly to have larger Schottky barrier height and smaller insulator thickness, as well. And it would also be helpful for you to keep in mind that type-A is black-colored, B blue, C green and D red-colored, in the following whole presentation. InP InP tins = 11 nm B = 0.7 eV InAlAs InAlAs tins = 7 nm B = 0.8 eV InGaAs InGaAs Pt/Ti/Au on InAlAs : Type C Buried Pt on InAlAs : Type D

Output characteristics for InGaAs HEMTs Ti on InP Ti on InAlAs Pt on InAlAs Buried Pt on InAlAs This shows output characteristics for the fabricated all types of InGaAs HEMTs, which have three different gate lengths. Solid line is for 150, dashed line for 100 and marked line for 50 nm, respectively. Ti-Schottky on InP etch-stopper device exhibits the worst scaling and pinch-off characteristics, because of the huge gate leakage current, as a result from the lowest Schottky barrier height. On the contrary, the other three types of devices exhibit pretty good output characteristics. Especially, buried Platinum on InAlAs device, shows a little bit better scaling characteristics and less short-channel effects, such as less negative shift of the threshold voltage, as increasing drain bias. Next, let me show you transconductance characteristics of these all devices, so that we can investigate the scaling and modulation behaviors further.

Gm characteristics for 50 nm InGaAs HEMTs This shows transconductance characteristics for all 50 nm InGaAs HEMTs at the drain bias of .5. As you can see in this figure, it is clear that maximum transconductance improves as the insulator thickness decreases. Specifically, Buried Pt device exhibits the best modulation capability, such as GM,max of 1.5 S/mm, even with .5 supply voltage. If we also focus on these two characteristics with the same insulator thickness such as Ti and Pt on InAlAs, we can easily see that the increase of Schottky barrier height enables the device’s VT to be shifted in the positive direction. If we look at subthreshold characteristics, we are able to realize exactly how much the device’s Schottky barrier height and insulator thickness would affect to the device’s logic characteristics. Ti on InP Ti on InAlAs Pt on InAlAs Buried Pt on InAlAs tins [nm] 17 11 7 GM,max [S/mm] 1.1 1.3 1.5

Subthreshold characteristics for 50 nm InGaAs HEMTs This shows semi-log plot of the measured drain and gate current as a function of VGS at the drain bias of .5, for all types of 50 nm InGaAs HEMTs. These four marked lines are for ID and dashed lines for IG, respectively. Here, we can see that subthreshold leakage current, in InGaAs HEMTs operation, is mostly limited by gate leakage current through Schottky junction. Apparently, the direction from left to right is exactly to have higher B and smaller insulator thickness, which exhibits a significant improvement in subthreshold characteristics, such as the improved subthreshold leakage level and subthreshold slope characteristics. From now on, I am going to do the detailed analysis for the device’s logic characteristics. B   improvement in subthreshold characteristics tins 

Evaluation Methodology Methodology of Chau (T-Nano 2005) VCC = 0.5 V ION 3 1 VCC ID [mA/mm] 1 mA/mm 3 2 VCC IOFF VT VGS This shows the evaluation methodology, which we have utilized in this study. In estimating the logic characteristics of novel devices which have non-optimized threshold voltage, we have to pay attention to avoid erroneous and physically meaningless values of logic parameters. For example, arbitrary selection of VT and ION often results in over-estimation of ION/IOFF ratio, in our InGaAs HEMT. In this study, we have followed the method proposed by Dr. Robert Chau. First, we selected gate-to-source voltage reaching at 1mA/mm of Id as the threshold voltage. Then we selected ION as 2/3 VCC swing above the threshold voltage, and IOFF as 1/3 VCC swing below the threshold voltage. Based on this definition, we extracted and compared the device’s all logic parameters, such as subthreshold slope, DIBL and ION/IOFF ratio for all types of our InGaAs HEMTs - VT at ID = 1 mA/mm & S = 1/Slope(VGS=VT, VDS=VCC) - DIBL = [VT (VDS = VCC) - VT (VDS = 0.05)] / VCC - 0.05 2 3 - ION = ID (VGS = VT + VCC, VDS = VCC) 1 3 - IOFF = ID (VGS = VT − VCC, VDS = VCC)

DIBL, S & ION/IOFF for 50 nm InGaAs HEMTs VT [V] DIBL [mV/V] S [mV/dec] ION/IOFF Ti on InP -1.1 300 200 63 Ti on InAlAs -0.65 220 130 1  10 3 Pt on InAlAs -0.55 180 100 7.2  10 3 Buried Pt on InAlAs -0.20 160 86 1.7  10 4 This shows semi-log plot of the measured ID as a function of VGS at the VCC of .05 and .5, for all our 50 nm InGaAs HEMTs. As we improve Schottky barrier height and gate-to-channel aspect ratio, the device’s threshold voltage moves along the positive. At the same time, all the device’s logic parameters, such as DIBL, subthreshold slope and ION/IOFF ratio, are remarkably improved. In particular, we were able to get as low as DIBL and subthreshold slope of 160 and 86, and as high as ION/IOFF ratio of 17 thousand, for Buried Platinum on InAlAs. At this moment, I’d like to remind you that the original purpose of all these devices was to improve high speed characteristics such as cutoff frequency fT and maximum oscillation frequency fmax, not logic performance. Nonetheless, our InGaAs HEMT, especially Buried Platinum device, which was not well optimized for logic application, exhibits excellent logic performance.

fT Scaling  Poor scalability of GM & GO due to short-channel effects CPGD (de-embedded) Record fT (Fujitsu) RS & RD (de-embedded) This shows fT scaling of our InGaAs HEMTs. Besides characterizing the logic performance from the static measurements, it is very useful to investigate fT characteristics as a function of gate length, in order to further clarify the short channel effect of InGaAs HEMTs. As you can see in this figure, the red colored buried Platinum device exhibits a little bit better fT scaling property, though all types of our InGaAs HEMTs suffer from severe deviation of fT dependency from the ideal 1/Lg slope. Another red colored curves represent fT dependency after de-embedding the parasitic resistances and parasitic gate-to-drain feedback capacitance from Buried Platinum device, where we can see that these parasitics should also play an important role as scaling down. From these results, our understanding for fT scaling is that a large deviation of fT dependency from the ideal 1/Lg slope is originated not only by short channel effect including no further improvement of transconductance and degradation of output conductance as scaling down, but also by relatively increased impact of extrinsic components, such as parasitic resistance and parasitic capacitance.  Poor scalability of GM & GO due to short-channel effects  Impact of parasitics : RS & RD & CPDG

Contents Introduction Fabrication of InGaAs HEMTs Characterization of InGaAs HEMTs Logic Parameters Scaling Limit Benchmarking against Si MOSFETs Conclusions Next, I’m going to benchmark this technology against advanced Si MOSFETs. Specifically, I will compare the logic performance of InGaAs HEMTs to that of Si-MOSFET, in terms of subthreshold slope, cutoff frequency, and gate delay.

Subthreshold Slope Here I plot the extracted subthreshold slope of our InGaAs HEMTs as a function of gate length at the VCC of .5. I also include that of planar-type Si MOSFETs, for comparison. As shown in this figure, these two devices with the same insulator thickness, exhibit poor subthreshold slope characteristics. Even in both devices, the choice of Platinum as Schottky contact, which has higher metal work-function than that of Ti, enables to improve subthreshold slope characteristics. More importantly, improving schottky barrier height and gate-to-channel aspect ratio, by means of Buried Platinum formation, eventually enables Buried Platinum device to exhibit a little better subthreshold slope, than advanced Planar type Si MOSFETs.  Buried Pt InGaAs HEMTs exhibits S equivalent to Si MOSFETs < Ref. : Chau et al. (T-Nano 2005) >

fT – Power Tradeoff 2.2  13  This shows tradeoff between fT and Power dissipation Here, I plot cutoff frequency as a function of DC power dissipation for 50 and 100 nm Buried Platinum device at the VCC of .5 as well as physical gate length 80 nm Si-MOSFET at the VCC of .7. As shown in this figure, our InGaAs HEMTs exhibit 13 times lower DC power dissipation for the equivalent fT, and 2.2 times higher fT at the same DC power dissipation, even with almost 30 times lower supply voltage of .5. And these phenomenon are mainly attributed to higher channel mobility of our InGaAs HEMTs.  InGaAs HEMTs show low power & high speed characteristics! < Ref. : Kuhn et al. (VLSI 2004) >

Dependency of Logic Parameters on VT Methodology of Lundstrom (IEDM, 2004) 1 2   VCC VCC 3 3 ION’   ID [mA/mm] IOFF’ VT VT’ As I mentioned earlier, logic parameters of InGaAs HEMT are dependent very much upon the choice of VT. For more generalized characterization, Lundstrom at Purdue university proposed this kind of methodology, in his CNT device analysis, as shown in the left figure. For example, varying VT creates a new set of logic parameters, including ION/IOFF ratio. The right figure is the plot of the re-extracted ION/IOFF ratio while VT moves along the ID curve. As we move VT along this direction, ION increases slowly while IOFF continues to increase exponentially. Therefore, the net ION/IOFF ratio drops quickly, which explains this dependency. On the contrary, in the opposite direction, IOFF becomes a limiting factor in ION/IOFF ratio because of gate leakage current through Schottky junction, which also explains this dependency. As a result, we have found that ION/IOFF ratio has monotonic behavior upon the difference between threshold voltages in our all InGaAs HEMTs. It is also clear that buried Pt device exhibits the widest range of threshold voltages above 10 to 4 of ION/IOFF ratio. Interestingly, we can find that the peak ION/IOFF ratios almost coincide with VT definition of 1 mA/mm, which could demonstrate that this definition has enough physical meaning in the logic performance analysis of InGaAs HEMTs. VGS  Varying VT definition maps tradeoff between ION/IOFF and CV/I  Useful to explore suitability of novel devices with non-optimized VT

GATE DELAY vs. ION/IOFF Chau’s approach to gate delay: VT’ – VT < 0 VT = VT’ @ 1 mA/mm VT’ – VT > 0 Here is the plot of the extracted gate delay, so called CV/I, as a function of ION/IOFF ratio, which implies to vary threshold voltage, exactly as explained in the previous slide. In the extraction of gate delay, we have utilized Chau’s approach. C is total gate capacitance at VCC and ION bias point, which is determined from high frequency S-parameters. V is equal to VCC and I to ION, respectively. These emphasized marks correspond to VT definition of 1 mA/mm. All of our 50 nm InGaAs HEMTs have quite similar values of gate delay, around .6 psec at the VCC of .5, but, a more important thing is that our Buried Platinum device has much higher ION/IOFF ratio, at the same time. Chau’s approach to gate delay: C V (CGS + CGD)  VCC  = VCC, ION I ION

GATE DELAY vs. ION/IOFF Finally, I compare the gate delay of our 50 nm InGaAs HEMT to the state of the art 40 nm Si NMOS as well as another type of the former speaker’s InSb HEMT with much higher channel mobility. In the right figure, I also compare the gate delays of these three technologies as a function of gate length. Though we have utilized non-optimized InGaAs HEMTs as a vechile, we can see that our 50 nm InGaAs HEMTs exhibit as low as logic gate delay of .66 psec with high enough ION/IOFF ratio at the VCC of .5, which is much lower than general Si MOSFET with the same gate length and even lower than the-state-of-the-art 40 nm Si-MOSFET  For 50 nm InGaAs HEMTs, CV/I = 0.66 ps @ VCC = 0.5 V < Ref. : Chau et al. (T-Nano 2005) >

Conclusions Enhancing B and shrinking tins essential for good logic performance of InGaAs HEMTs Logic performance of 50 nm InGaAs HEMTs: ION/IOFF > 104, S < 86 mV/dec, DIBL = 160 mV/V @ VCC = 0.5 V For ION/IOFF = 104, gate delay < 1 ps @ VCC = 0.5 V Comparable to state of the art MOSFETs Future options of InGaAs HEMTs for logic application E-mode operation, MIS structure & self-aligned scheme In conclusion, we have clearly shown that enhancing schottky barrier height and shrinking insulator thickness were essential for good logic performance. Even with non-optimized 50 nm InGaAs HEMTs, we were able to get these excellent logic characteristics even at the VCC of .5 V, such as ION/IOFF ratio of above 10 to 4, subthreshold slope of less than 86 mV/dec, and DIBL of 160 mV/V. With further device optimization, InGaAs HEMTs could well be the choice as a beyond CMOS logic technology. Hopely, we could demonstrate some results, based on these future options, such as e-mode operation, MIS structure and self-aligned scheme. Thank you very much for your careful attention!