Blame Passing for Analysis and Optimisation

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Presentation transcript:

Blame Passing for Analysis and Optimisation Charlie Brej APT Group University of Manchester 16/11/2018 Async Forum

Overview Introduction Synchronous methods Blame passing Optimisations Results 16/11/2018 Group Talk

Why we need optimisation High level entry languages RTL Gates Transistors Silicon Large designs More important things to worry about Optimal designs often difficult to read Difficult to determine inefficiencies 16/11/2018 Group Talk

Critical path analysis 1 2 3 4 5 16/11/2018 Group Talk

Retiming 16/11/2018 Group Talk

Why we don’t use the Critical Path Assumes isochronic arrival of all inputs in each stage Or predictable sequencing and timing of arrival of inputs (deterministic) No cyclic circuits No C-elements Only looks at logic and not latches No method of determining the interaction between different computation cycles Determines and improves the worst (not average / “mode”) case performance 16/11/2018 Group Talk

Slowest Path Designed for asynchronous circuits Allows cyclic circuits Allows non-deterministic behavior Uses a real simulation Gathers average case data (not worst case) Sort of like critical path of a full benchmark Start point is the release of the reset End point is the benchmark completion signal 16/11/2018 Group Talk

Blame Game 2nd Place Output 1st Place Benchmark complete 16/11/2018 Group Talk

Blame Game 16/11/2018 Group Talk

Pass the blame Blame passing forms a path from completion back to reset release How to extract path Static timing analysis (cyclic paths) Simulation dump (lots of data) Use a custom simulator Small overhead (~30%) Only remember the slowest path transitions 16/11/2018 Group Talk

Decrementer while (1) { if (Reg != 0) Reg = Reg – 1; else Reg = Const; } 16/11/2018 Group Talk

Graphical representation 16/11/2018 Group Talk

Apply Optimisations Find known paths through elements Paths with positive effect Paths with negative effect Apply optimisation Simulate again to determine the effect 16/11/2018 Group Talk

Optimisation Rules 16/11/2018 Group Talk

Optimisation Rules 16/11/2018 Group Talk

Optimisation Rules 16/11/2018 Group Talk

Optimisation Results (Dec) 16/11/2018 Group Talk

Optimisation Results (GCD) 16/11/2018 Group Talk

Optimisation Results (MIPS) 16/11/2018 Group Talk

Conclusions Novel analysis and optimisation technique Applicable to many asynchronous systems Not just circuits Automatic reanalysis system Future work: Read SDF files Extension to other systems (Balsa etc) Connection to a full design system (Biscotti) 16/11/2018 Group Talk