VCSEL drivers in ATLAS Optical links Futian Liang @2014第三届核电子学ASIC研讨会，2014.4.23，IHEP

Outlines Optical links in ATLAS The fastest VCSEL driver in HEP LOCld1 Challenge / Goal LOCld1 Structure / Optical test/ BERT / Irradiation LOCld1V2 I2C / DAC / Irradiation Work presented here is from a collaboration among USTC (Futian Liang), CCNU (Xiaoting Li) and SMU (Datao Gong, et al.)

Optical links in ATLAS Most of the commercial equipment / devices / microchips CANNOT survival in the radiation environments.

The fastest VCSEL driver in HEP Challenge GBLD (CERN, 2012) is designed for 5 Gbps, and measures to 5 Gbps with 0.13um CMOS process. Silicon-on-Sapphire (SoS) CMOS process (0.25um). Goal 2 mA CML input, 8 mA output AC to VCSEL 8 Gbps transmission data rate radiation tolerant / hard

LOCld1: Structure details 4. AC coupled VCSEL with bias current 6. 3.3 V power & peaking strength control 5. Differential output, 8 mA max modulation 7. Input impedance match & common voltage 8. Input CML, 2 mA minimum Here is the block diagram of LOCld1. 9. Tail current reference 3. Bias current with control 1. Six pre-drive stages with active shunt peaking 2. Differential output stage with 50  pull-up [1] Liang F, Gong D, Hou S, et al. The design of 8-Gbps VCSEL drivers for ATLAS liquid Argon calorimeter upgrade[J]. Journal of Instrumentation, 2013, 8(01): C01031. [2] Fu-Tian L, Datao G, Suen H, et al. Active inductor shunt peaking in high-speed VCSEL driver design[J]. Chinese Physics C, 2013, 37(11): 116101.

Optical test <-5 Gbps with 4.25 Gbps Eye mask our design has a lot of margin. 8 Gbps with 4.25 Gbps Eye mask ---------------> No hit in 3 mask areas with 3000 waveforms.

LOCld1 optical Bit Error Rate Test Chip Electrical bit error rate test system VCSEL transmitter Optical receiver

LOCld1 optical Bit Error Rate Test 300s@5Gbps, pass, BER<6.667x10-13 300s@8Gbps, pass, BER<4.167x10-13 300s@10Gbps, pass, BER<3.33x10-13 15h@10Gbps, pass, 6 errors in 5.4x1014bits, BER=1.11x10-14 300s@10.5Gbps, pass, 3 errors in 3.15x1012bits, BER=9.524x10-13 The design target is 8Gbps

Irradiation / X-ray shows the 8-Gbps eye diagram before irradiation. After a period of irradiation, It’s obviously the eye diagram is damaged, and both of the bias and modulation current of the eye diagram become smaller we need a one time adjustment of the bias current and modulation current, and then it’s stable. shows the eye diagram after a long-time irradiation, we can see the eye diagram is almost same with the one in (c).

LOCld1V2 0.7 mm x1.9 mm Imod and Ibias are adjusted via two 4-bit current DAC. Vp is programmable via a 5-bit voltage DAC. All three DACs are configured via an on-chip I2C slave module. In order to be immune to single-event upsets, 16-bit internal registers are protected with Triple Modular Redundancy (TMR).

MTx LOCld version Test MTX module Truelight 10G VESEL TTF-1F59-427 LOCld1v2 VESEL driver chip Carrier board with MTx module CENTELLAX PCB12500 BERT Carrier MTx Tektronix TDS8000B Scop Coaxial Cable Fiber Test setup MTx is the world’s smallest TOSA based optical transmitter with little material, also suitable for inner tracker applications.

Input : 8Gbps PRBS7, 200mVp-p Vpk = 2.25 V, Imod = 6.4 mA, Ibias = 6 mA Board #1 Board #2 Board #3 Channel #1 Channel #1 Channel #1 Channel #2 Channel #2 Channel #2

Input : 10Gbps PRBS7, 200mVp-p Vpk = 2.25 V, Imod = 6.4 mA, Ibias = 6 mA Board #1 Board #2 Board #3 Channel #1 Channel #1 Channel #1 Channel #2 Channel #2 Channel #2

X-ray irradiation test setup PCB12500 PRBS7 8Gbps 330 mV pk-pk -10dB attenuator + DC block 200 mV pk-pk 1.5 m coaxial cables LOCld1V2 MTX Board #2 22m Multimode fiber TDS8000B Sampling Scope Trig clock 1GHz Power Supply 3.3 V 2.5 V Part in red color is under x-ray beam The tested MTX board is board #2 and the carrier board is also board #2

Day 1 Notes are on the next page a. start b. 10 sec c. 30 sec d. 2 min 13 sec e. 10 min f. adjust Vp = E8 (2.4 V) g. 40 min h. left moving of g i. 1 hour 40 min

Day 1 i. 1 hour 40 min j. 3 hour 40 min Configuration at start: Vp = C8h, Imod = 0h, Ibias = 4h; That is: Vp = 2.25 V, Imod = 6.4 mA, Ibias = 6 mA; The names under each plots are the total time of irradiation After adjusting in plot f (which is after 10-min irradiation), we changed Vp to E8h, which is equal to 2.4 V, keeping Imod and Ibias original After 40-min (total) irradiation, the shapes of the eye diagrams are almost constant, while their horizontal positions keep on moving

Day 2 a. start b. 1 hour c. 4 hour 36 min d. 7 hour 47 min e. left moving of d f. vertically re-scaled Configuration of day 2 is : Vp = E8h, Imod = 0h, Ibias = 4h; That is: Vp = 2.4 V, Imod = 6.4 mA, Ibias = 6 mA; The names under each plots are the total time of irradiation The shapes of the eye diagrams are almost constant, while their horizontal positions keep on moving

Summary LOCld1v2 The fastest VCSEL driver in HEP designed for 8 Gbps, measures up to 10 Gbps Configure with I2C meet the radiation requirements for ATLAS LAr application

Thank you! & We will do more & better!

Backup slides followed

I took 1.33mm2 (15%) area and 42 (30%) round pin 3mm X 3mm 144 round pins TRNG(Yellow) 550um X 1150um LOCld (White) LOCld1 320um X 500um LOCld4 450um X 1200um I took 1.33mm2 (15%) area and 42 (30%) round pin 看电感的面积。