CMPE 382 / ECE 510 Computer Organization & Architecture Appendix A- Pipelining based on text: Computer Architecture : A Quantitative Approach (Paperback) John L. Hennessy, David A. Patterson Morgan Kaufmann; 4th edition 2006 Many lecture slides are courtesy of or based on the work of Drs. Asanovic, Patterson, Culler and Amaral CS252 S05

5 Steps of MIPS Datapath Figure A.3, Page A-9 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Imm WB Data RD RD RD Data stationary control local decode for each instruction phase / pipeline stage cmpe382/ece510 ch A CS252 S05

Visualizing Pipelining Figure A.2, Page A-8 Time (clock cycles) Reg ALU DMem Ifetch Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7 Cycle 5 I n s t r. O r d e cmpe382/ece510 ch A CS252 S05

Pipeline Stages We can divide the execution of an instruction into the following 5 “classic” stages: IF: Instruction Fetch ID: Instruction Decode, register fetch EX: Execution MEM: Memory Access WB: Register write Back cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns Consider the pipeline above with the indicated delays. We want to know what is the pipeline throughput and the pipeline latency. Pipeline throughput: instructions completed per second. Pipeline latency: how long does it take to execute a single instruction in the pipeline. cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns Pipeline throughput: how often an instruction is completed. Pipeline latency: how long does it take to execute an instruction in the pipeline. Is this right? cmpe382/ece510 ch A CS252 S05

Asynchronous Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns Simply adding the latencies to compute the pipeline latency, only would work for an isolated instruction IF MEM ID I1 L(I1) = 28ns EX WB IF I2 L(I2) = 33ns ID EX MEM WB MEM ID IF I3 L(I3) = 38ns EX WB MEM ID IF I4 EX WB L(I5) = 43ns We are in trouble! The latency is not constant. This happens because this is an unbalanced pipeline. The solution is to make every state the same length as the longest one. cmpe382/ece510 ch A CS252 S05

Synchronous Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns The slowest pipeline stage also limits the latency!! I1 IF ID EX MEM WB I2 L(I2) = 50ns IF ID EX MEM WB I3 IF ID EX MEM WB I4 IF ID EX MEM 10 20 30 40 50 60 L(I1) = L(I2) = L(I3) = L(I4) = 50ns cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns How long does it take to execute (issue) 20000 instructions in this pipeline? (disregard pipeline filling, bubbles caused by branches, cache misses, hazards) How long would it take using the same modules without pipelining? cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 10 ns Thus the speedup that we got from the pipeline is: How can we improve this pipeline design? We need to reduce the unbalance to increase the clock speed. cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM1 MEM2 WB 5 ns 4 ns 5 ns 5 ns 5 ns 4 ns Now we have one more pipeline stage, but the maximum latency of a single stage is reduced in half. The new latency for a single instruction is: cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM1 MEM2 WB 5 ns 4 ns 5 ns 5 ns 5 ns 4 ns I1 IF ID EX MEM1 MEM1 WB I2 IF ID EX MEM1 MEM1 WB I3 IF ID EX MEM1 MEM1 WB I4 IF ID EX MEM1 MEM1 WB I5 IF ID EX MEM1 MEM1 WB I6 IF ID EX MEM1 MEM1 WB I7 IF ID EX MEM1 MEM1 WB cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM1 MEM2 WB 5 ns 4 ns 5 ns 5 ns 5 ns 4 ns How long does it take to execute 20000 instructions in this pipeline? (disregard latency, bubbles caused by branches, cache misses, pipeline fill, etc, for now) Thus the speedup that we get from the pipeline is: cmpe382/ece510 ch A CS252 S05

Pipeline Throughput and Latency IF ID EX MEM1 MEM2 WB 5 ns 4 ns 5 ns 5 ns 5 ns 4 ns What have we learned from this example? 1. It is important to balance the delays in the stages of the pipeline 2. The throughput of a pipeline is 1/max(delay). 3. The latency is Nmax(delay), where N is the number of stages in the pipeline. cmpe382/ece510 ch A CS252 S05

One Memory Port/Structural Hazards Figure A.4, Page A-14 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 ALU I n s t r. O r d e Load Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 1 Reg ALU DMem Ifetch Instr 2 ALU Instr 3 Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 4 cmpe382/ece510 ch A CS252 S05

One Memory Port/Structural Hazards (Similar to Figure A.5, Page A-15) Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 ALU I n s t r. O r d e Load Ifetch Reg DMem Reg Reg ALU DMem Ifetch Instr 1 Reg ALU DMem Ifetch Instr 2 Bubble Stall Reg ALU DMem Ifetch Instr 3 How do you “bubble” the pipe? cmpe382/ece510 ch A CS252 S05

Pipelining is not quite that easy! Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). cmpe382/ece510 ch A CS252 S05

Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1: cmpe382/ece510 ch A CS252 S05

Data Hazard on R1 Figure A.6, Page A-17 Time (clock cycles) IF ID/RF EX MEM WB I n s t r. O r d e add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMem Ifetch cmpe382/ece510 ch A CS252 S05

Three Generic Data Hazards Read After Write (RAW) InstrJ tries to read operand before InstrI writes it Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. I: add r1,r2,r3 J: sub r4,r1,r3 cmpe382/ece510 ch A CS252 S05

Three Generic Data Hazards Write After Read (WAR) InstrJ writes operand before InstrI reads it Called an “anti-dependence” by compiler writers. This results from reuse of the name “r1”. Can’t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5 I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 cmpe382/ece510 ch A CS252 S05

Three Generic Data Hazards Write After Write (WAW) InstrJ writes operand before InstrI writes it. Called an “output dependence” by compiler writers This also results from the reuse of name “r1”. Can’t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in more complicated pipes I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 cmpe382/ece510 ch A CS252 S05

Forwarding to Avoid Data Hazard Figure A.7, Page A-19 Time (clock cycles) I n s t r. O r d e add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMem Ifetch cmpe382/ece510 ch A CS252 S05

HW Change for Forwarding Figure A.23, Page A-37 ID/EX EX/MEM MEM/WR NextPC mux Registers ALU Data Memory mux mux Immediate What circuit detects and resolves this hazard? cmpe382/ece510 ch A CS252 S05

Forwarding to Avoid LW-SW Data Hazard Figure A.8, Page A-20 Time (clock cycles) I n s t r. O r d e add r1,r2,r3 lw r4, 0(r1) sw r4,12(r1) or r8,r6,r9 xor r10,r9,r11 Reg ALU DMem Ifetch cmpe382/ece510 ch A CS252 S05

Data Hazard Even with Forwarding Figure A.9, Page A-21 Time (clock cycles) Reg ALU DMem Ifetch I n s t r. O r d e lw r1, 0(r2) sub r4,r1,r6 and r6,r1,r7 or r8,r1,r9 MIPS actutally didn’t interlecok: MPU without Interlocked Pipelined Stages cmpe382/ece510 ch A CS252 S05

Data Hazard Even with Forwarding (Similar to Figure A.10, Page A-21) Time (clock cycles) I n s t r. O r d e Reg ALU DMem Ifetch lw r1, 0(r2) Reg Ifetch ALU DMem Bubble sub r4,r1,r6 Ifetch ALU DMem Reg Bubble and r6,r1,r7 Bubble Ifetch Reg ALU DMem or r8,r1,r9 How is this detected? cmpe382/ece510 ch A CS252 S05

Mental Exercise How could you implement forwarding with software/compiler assistance, rather than hardware detection of the hazard? (Still requires multiplexors) cmpe382/ece510 ch A CS252 S05

Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d ,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd Compiler optimizes for performance. Hardware checks for safety. cmpe382/ece510 ch A CS252 S05

Why the fast code is faster? cmpe382/ece510 ch A CS252 S05

Mental Exercise – software forwarding Do forwarding under software control Assign special register names (R28-R30) to previous, previous2 ALU result, memory read Reduces register file size by 3, unfortunately Saves hardware Software (compiler) is cheap Good or bad idea? What are some of the costs? cmpe382/ece510 ch A CS252 S05

Mental Exercise – Problems with software solution People like sequential consistency code should behave as if each instruction completes before next instruction is issued Interrupts – previous instructions may not have their data on the fly if an interrupt occurred between them ISA must be dedicated to one pipeline implementation, old object code wouldn't run cmpe382/ece510 ch A CS252 S05

Control Hazard on Branches Three Stage Stall Reg ALU DMem Ifetch 10: beq r1,r3,36 14: and r2,r3,r5 18: or r6,r1,r7 22: add r8,r1,r9 36: xor r10,r1,r11 What do you do with the 3 instructions in between? How do you do it? Where is the “commit”? cmpe382/ece510 ch A CS252 S05

Branch Stall Impact If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9! Two part solution: Determine branch taken or not sooner, AND Compute taken branch address earlier Early MIPS branch tests if register = 0 or  0 MIPS Solution: Move Zero test to ID/RF stage Adder to calculate new PC in ID/RF stage 1 clock cycle penalty for branch versus 3 cmpe382/ece510 ch A CS252 S05

Pipelined Early MIPS Datapath Figure A.24, page A-38 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC ID/EX EX/MEM MEM/WB MUX 4 Adder IF/ID Adder Zero? RS1 Address Reg File Memory RS2 ALU Memory Data MUX MUX Sign Extend Imm WB Data RD RD RD Interplay of instruction set design and cycle time. cmpe382/ece510 ch A CS252 S05

Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken Execute successor instructions in sequence “Squash” instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken 53% MIPS branches taken on average But haven’t calculated branch target address in MIPS MIPS still incurs 1 cycle branch penalty Other machines: branch target known before outcome cmpe382/ece510 ch A CS252 S05

Four Branch Hazard Alternatives #4: Delayed Branch Define branch to take place AFTER a following instruction branch instruction sequential successor1 sequential successor2 ........ sequential successorn branch target if taken 1 slot delay allows proper decision and branch target address in 5 stage pipeline MIPS uses this Branch delay of length n cmpe382/ece510 ch A CS252 S05

Scheduling Branch Delay Slots (Fig A.14) A. From before branch B. From branch target C. From fall through add $1,$2,$3 if $2=0 then add $1,$2,$3 if $1=0 then sub $4,$5,$6 delay slot delay slot add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes if $2=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 add $1,$2,$3 if $1=0 then sub $4,$5,$6 Limitations on delayed-branch scheduling come from 1) restrictions on the instructions that can be moved/copied into the delay slot and 2) limited ability to predict at compile time whether a branch is likely to be taken or not. In B and C, the use of $1 prevents the add instruction from being moved to the delay slot In B the sub may need to be copied because it could be reached by another path. B is preferred when the branch is taken with high probability (such as loop branches A is the best choice, fills delay slot & reduces instruction count (IC) In B, the sub instruction may need to be copied, increasing IC In B and C, must be okay to execute sub when branch fails cmpe382/ece510 ch A CS252 S05

Delayed Branch Compiler effectiveness for single branch delay slot: Fills about 60% of branch delay slots About 80% of instructions executed in branch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches Growth in available transistors has made dynamic approaches relatively cheaper cmpe382/ece510 ch A CS252 S05

Evaluating Branch Alternatives Assume 4% unconditional branch, 6% conditional branch- untaken, 10% conditional branch-taken Scheduling Branch CPI speedup v. speedup v. scheme penalty unpipelined stall Stall pipeline 3 1.60 3.1 1.0 Predict taken 1 1.20 4.2 1.33 Predict not taken 1 1.14 4.4 1.40 Delayed branch 0.5 1.10 4.5 1.45 cmpe382/ece510 ch A CS252 S05

Static (compiler) branch prediction Use static prediction (compiler), squash speculatively executed instructions if necessary Branch-likely, Branch-not-likely instructions BEQL, BNEL “obsolete” in MIPS R4000 BEQ, BNE already predicted “not-taken” Compiler can predict some branch outcomes Profiling with representative data can predict more outcomes But, data may change over time ... cmpe382/ece510 ch A CS252 S05

Dynamic Branch Prediction e.g. 256 instructions on the fly (8-issue x 32 deep) Huge cost to mispredict Need to do better than 56% Predict based on past history Speculatively execute most-likely code (branch taken / not-taken) squash write-back or commit stage if branch target guessed wrong cmpe382/ece510 ch A CS252 S05

Problems with Pipelining Exception: An unusual event happens to an instruction during its execution Examples: divide by zero, undefined opcode Interrupt: Hardware signal to switch the processor to a new instruction stream Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting) Problem: It must appear that the exception or interrupt must appear between 2 instructions (Ii and Ii+1) The effect of all instructions up to and including Ii is totaling complete No effect of any instruction after Ii can take place The interrupt (exception) handler either aborts program or restarts at instruction Ii+1 cmpe382/ece510 ch A CS252 S05

Precise Exceptions In-Order Pipelines Key observation: architected state only change in memory and register write stages. CS252 S05

Mismatched Pipeline Lengths FP pipelines are often different length to integer Different instructions have different throughputs (initiation intervals) e.g. FPadd throughput=1, FPdivide throughput=1/25 cycles WAW, WAR, RAW hazards, look out Instructions issued in order can now complete out of order Hardware (or rarely, compiler) must monitor and avoid hazards Multiple instructions may want to perform WB in single cycle -- New structural hazard What if an earlier instruction never completes? cmpe382/ece510 ch A CS252 S05

Interrupts and Exceptions Need to resume (carry on) after an exception At what program counter value? Between instructions IO device request Invoke OS, tracing, breakpoints Stall until all previously issued instructions have completed Resume with instruction at next PC Within an instruction ALU overflow, NaN, etc. Memory page fault or violation, unsupported misaligned access Power failure interrupt Similar: Mispredicted speculative execution (branches) Recovery gets tense if out of order execution is permitted cmpe382/ece510 ch A CS252 S05

What state changes in these instructions? Using CISC addressing modes ADD R1,(R2)++ STORE R1,--(R3) cmpe382/ece510 ch A

Recovery from Exceptions Within Instructions 68000 – page fault not supported in processor Buy a second processor and run it ~1 instruction behind the first. If the primary processor encounters an exception, interrupt the second processor and recover clean state from it. 68012, 68020, 68030 take a snapshot of processor internal state, including pipeline (~40 words in addition to documented user state), write state out to stack Harder to recover because instructions have multiple destinations (e.g. autoincrement address mode) Restart instructions from the middle cmpe382/ece510 ch A CS252 S05

Recovery from Exceptions Within Instructions Keep an in-order register-value history “history file” restore register values from history pretend out-of-order completion of instructions never happened restart instructions from first one that did not complete “Future file” Instruction results saved in future file and not committed to “real” registers until previous instructions complete Force in-order completion easy in 5-stage pipeline, act as if started instructions never happened, omit memory-write and write-back (single destination per instruction) performance hit in complex pipelines Register renaming cmpe382/ece510 ch A CS252 S05

Imprecise Exceptions No simple return-from-interrupt instruction Keep a hardware list of instructions that have completed Simulate completion of missing instructions in OS software Return to PC where all remaining instructions have yet to be executed How to stop debugging from becoming a nightmare? Synchronize instruction stall until all issued instructions can no longer generate an exception cmpe382/ece510 ch A CS252 S05

MIPS R4400 “superpipelined”, 8 clock cycles instead of 5 2+ cycles for instruction fetch 3 cycles for data memory load/store Result of load speculatively available pending cache tag check FP latency 2 .. 112 cycles cmpe382/ece510 ch A CS252 S05

What's needed to oversee correct out-of-order instruction completion? Get complier to detect problems, static scheduling problems for pipeline upgrades? Detect when result is available (RAW) Detect when done with source (WAR) Detect when done with destination (WAW) cmpe382/ece510 ch A CS252 S05

Scoreboard for out-of-order execution In-order instruction issue Bypass instructions that must stall before operand fetch, allowing another instruction to get started Execute out of order Scoreboard keeps record of data dependencies between instructions controls safe initiation of operand fetch and execution controls when result can safely be written No ability to eliminate dependencies through register renaming cmpe382/ece510 ch A CS252 S05

Summary: Metrics and Pipelining Machines compared over many metrics Cost, performance, power, reliability, compatibility, … Difficult to compare widely differing machines on benchmark suite Control VIA State Machines and Microprogramming Just overlap tasks; easy if tasks are independent Speed Up  Pipeline Depth; if ideal CPI is 1, then: Hazards limit performance on computers: Structural: need more HW resources Data (RAW,WAR,WAW): need forwarding, compiler scheduling Control: delayed branch, prediction Exceptions, Interrupts add complexity cmpe382/ece510 ch A CS252 S05