Multiplexer Implementation of Digital Logic Functions

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Presentation transcript:

Multiplexer Implementation of Digital Logic Functions Dr. Bhanu Bhaskara NMR Engineering College Hyderabad

FPGA Architecture

Xilinx CLB

Xilinx Spartan FPGA

Digital Logic Functions Combinational Logic Implemented using Gates NAND Implementations Sequential Logic Consists of Flip Flops Inside - NAND gates NAND gate using MUX?

MUX with NAND F = (p.q)'

2:1 Mux F = s’ p + s q 1 p q s F

2:1 Mux G = a’ + b’ G = a’ + a b’ G = a’.1 + a. b’ F = s’ p + s q 1 p 1 p q s F G = a’ + b’ G = a’ + a b’ G = a’.1 + a. b’ F = s’ p + s q 1 G b’ 1 a

Output? U a 1 1 W C’ 1 1 V b’ D E

Configurable? U ? ? 1 W ? 1 1 V ? ? ? ?

See you Guys in the next class!