timing_type : recovery_rising;

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Presentation transcript:

timing_type : recovery_rising; RECOVERY TIMING CHECK Recovery timing check ensures that there is a minimum amount of time between the asynchronous signal becoming inactive and the next active clock edge. This recovery check is illustrated in below . pin(RSN) { . . . timing() { related_pin : "CK"; timing_type : recovery_rising; }

MULTIPLE CLOCKS INTEGER MULTIPLES: In this the multiple clocks are defined in a design with frequenciess that are simple multiples of each other. In this ,STA is performed by computing a common base period among all related clocks (two clocks are related if they have a data path between their domains). The common base period is established so that all clocks are synchronized. Below eg. Shows 4 related clocks: create_clock -name CLKM \ -period 20 -waveform {0 10} [get_ports CLKM] create_clock -name CLKQ -period 10 -waveform {0 5} create_clock -name CLKP \ -period 5 -waveform {0 2.5} [get_ports CLKP]

Fig.Integer multiple clocks A common base period of 20ns, as shown in above fig., is used when analyzing paths between the CLKP and CLKM clock domains

NON-INTEGER MULTIPLES Here the case is when there is a data path between two clock domains whose frequencies are not multiples of each other

The common period for data paths between CLKQ and CLKP is expanded to a base period of 10ns only. The common period for data paths between CLKM and CLKQ is 40ns, and the commonperiod for data paths between CLKM and CLKP is also 40ns. Fig .Set-up and hold checks for non-integer multiple clocks.

PHASE SHIFTED: Here two clocks are ninety degrees phase-shifted with respect to each other. create_clock -period 2.0 -waveform {0 1.0} [get_ports CKM] create_clock -period 2.0 -waveform {0.5 1.5} \ [get_ports CKM90]

The first rising edge of CKM90 at 0. 5ns is the capture edge The first rising edge of CKM90 at 0.5ns is the capture edge. The hold checkis for one cycle before the setup capture edge. For the launch edge at 2ns, the setup capture edge is at 2.5ns. Thus the hold check is at the previous capture edge which is at 0.5ns.